Verification Techniques for System-Level Design

A must-read in formal and semi-formal verification!

Masahiro Fujita (Author), Indradeep Ghosh (Author), Mukul Prasad (Author)

9780123706164, Elsevier Science

Hardback, published 12 December 2007

256 pages, Approx. 130 illustrations
23.4 x 19 x 2.1 cm, 0.67 kg

This book will explain how to verify SoC (Systems on Chip) logic designs using “formal? and “semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.

Subject Areas: Computer architecture & logic design [UYF], Computer security [UR], Electronic devices & materials [TJFD], Circuits & components [TJFC], Electronics engineering [TJF], Electrical engineering [THR], Technical design [TBD]