System-on-Chip Test Architectures
Nanometer Design for Testability

The comprehensive guide to modern system-on-chip testing and design for testability from bestselling author L.-T Wang!

Laung-Terng Wang (Author), Charles E. Stroud (Author), Nur A. Touba (Author)

9780123739735, Elsevier Science

Hardback, published 8 January 2008

896 pages, Approx. 600 illustrations
23.4 x 19 x 4.4 cm, 1.56 kg

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Introduction
Digital Test Architectures
Fault-Tolerant Design
SOC/NOC Test Architectures
SIP Test Architectures
Delay Testing
Low-Power Testing
Coping with Physical Failures, Soft Errors, and Reliability Issues
Design for Manufacturability and Yield
Design for Debug and Diagnosis
Software-Based Self-Testing
FPGA Testing
MEMS Testing
High-Speed I/O Interface
Analog and Mixed-Signal Test Architectures
RF Testing
Testing Aspects of Nanotechnology Trends.

Subject Areas: Automatic control engineering [TJFM], Microprocessors [TJFD1], Electronic devices & materials [TJFD], Circuits & components [TJFC], Electronics & communications engineering [TJ], Electrical engineering [THR], Technical design [TBD]