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Sigma-Delta Converters: Practical Design Guide
Jose M. de la Rosa (Author)
9781119275787, Wiley
Hardback, published 26 October 2018
576 pages
24.6 x 16.5 x 3.3 cm, 0.998 kg
Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), Σ∆Ms cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications. Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators—from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art Σ∆Ms. It makes more emphasis on two key points, which were not treated so deeply in the first edition: Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.
Preface xix Acknowledgements xxv List of Abbreviations xxvii 1 Introduction to ;;;; Modulators: Fundamentals, Basic Architecture and Performance Metrics 1 1.1 Basics of Analog-to-Digital Conversion 2 1.2 Sigma-Delta Modulation 9 1.3 The First-order ΣΔ Modulator 13 1.4 Performance Enhancement and Taxonomy of ΣΔMs 16 1.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs 19 1.6 ΣΔ DACs 22 1.7 Summary 25 References 26 2 Taxonomy of ;;;; Architectures 29 2.1 Second-order ΣΔ Modulators 30 2.2 High-order Single-loop ΣΔMs 35 2.3 Cascade ΣΔ Modulators 39 2.4 Multi-bit ΣΔ Modulators 49 2.5 Band-pass ΣΔ Modulators 55 2.6 Continuous-time ΣΔ Modulators: Architecture and Basic Concepts 64 2.7 DT–CT Transformation of ΣΔMs 70 2.8 Direct Synthesis of CT-ΣΔMs 74 2.9 Summary 76 References 76 3 Circuit Errors in Switched-capacitor ;;;; Modulators 83 3.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators 84 3.2 Finite Amplifier Gain in SC-ΣΔMs 86 3.3 Capacitor Mismatch in SC-ΣΔMs 90 3.4 Integrator Settling Error in SC-ΣΔMs 91 3.5 Circuit Noise in SC-ΣΔMs 101 3.6 Clock Jitter in SC-ΣΔMs 105 3.7 Sources of Distortion in SC-ΣΔMs 107 3.8 Case Study: High-level Sizing of a ΣΔM 111 3.9 Summary 119 References 119 4 Circuit Errors and Compensation Techniques in Continuous-time ;;;; Modulators 123 4.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators 123 4.2 CT Integrators and Resonators 124 4.3 Finite Amplifier Gain in CT-ΣΔMs 126 4.4 Time-constant Error in CT-ΣΔMs 128 4.5 Finite Integrator Dynamics in CT-ΣΔMs 130 4.6 Sources of Distortion in CT-ΣΔMs 134 4.7 Circuit Noise in CT-ΣΔMs 137 4.8 Clock Jitter in CT-ΣΔMs 140 4.9 Excess Loop Delay in CT-ΣΔMs 149 4.10 Quantizer Metastability in CT-ΣΔMs 155 4.11 Summary 159 References 160 5 Behavioral Modeling and High-level Simulation 165 5.1 Systematic Design Methodology of ΣΔ Modulators 165 5.2 Simulation Approaches for the High-level Evaluation of ΣΔMs 169 5.3 Implementing ΣΔM Behavioral Models 173 5.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-functions 188 5.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs 209 5.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs 216 5.7 Summary 231 References 231 6 Automated Design and Optimization of ;;;;Ms 235 6.1 Architecture Exploration and Selection: Schreier’s Toolbox 236 6.2 Optimization-based High-level Synthesis of ΣΔ Modulators 245 6.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs 255 6.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs 259 6.5 Summary 269 References 269 7 Electrical Design of ;;;;Ms: From Systems to Circuits 271 7.1 Macromodeling ΣΔMs 272 7.2 Examples of ΣΔM Macromodels 279 7.3 Including Noise in Transient Electrical Simulations of ΣΔMs 286 7.4 Processing ΣΔM Output Results of Electrical Simulations 294 7.5 Summary 298 References 298 8 Design Considerations of ;;;;M Subcircuits 301 8.1 Design Considerations of CMOS Switches 302 8.2 Design Considerations of Operational Amplifiers 308 8.3 Design Considerations of Transconductors 317 8.4 Design Considerations of Comparators 324 8.5 Design Considerations of Current-Steering DACs 332 8.6 Summary 338 References 338 9 Practical Realization of ;;;;Ms: From Circuits to Chips 341 9.1 Auxiliary ΣΔM Building Blocks 341 9.2 Layout Design, Floorplanning, and Practical Issues 348 9.3 Chip Package, Test PCB, and Experimental Setup 354 9.4 Experimental Test Set-Up 355 9.5 ΣΔM Design Examples and Case Studies 359 9.6 Summary 385 References 386 10 Frontiers, Trends and Challenges: Towards Next-generation ;;;; Modulators 389 10.1 State-of-the-Art ADCs: Nyquist-rate versus ΣΔ Converters 390 10.2 Comparison of Different Categories of ΣΔ ADCs 393 10.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 408 10.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion 415 10.5 Enhanced Cascade ΣΔMs 418 10.6 Power-efficient ΣΔM Loop-filter Techniques 423 10.7 Hybrid ΣΔM/Nyquist-rate ADCs 428 10.8 Time-based ΣΔ ADCs 431 10.9 DAC Techniques for High-performance CT-ΣΔMs 436 10.10 Classification of State-of-the-Art References 437 10.11 Summary and Conclusions 437 References 438 A State-space Analysis of Clock Jitter in CT-;;;;Ms 463 A.1 State-space Representation of NTF (z) 463 A.2 Expectation Value of (Δqn)2 465 A.3 In-band Noise Power due to Clock Jitter 466 References 467 B SIMSIDES User Guide 469 B.1 Getting Started: Installing and Running SIMSIDES 470 B.2 Building and Editing ΣΔM Architectures in SIMSIDES 470 B.3 Analyzing ΣΔMs in SIMSIDES 473 B.3.1 Node Spectrum Analysis 474 B.3.2 Integrated Power Noise 474 B.3.3 SNR/SNDR 475 B.3.4 Harmonic Distortion 475 B.3.5 Integral and Differential Non-Linearity 477 B.3.6 Multi-tone Power Ratio 477 B.3.7 Histogram 478 B.3.8 Parametric Analysis 478 B.3.9 Monte Carlo Analysis 479 B.4 Optimization Interface 480 B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs 482 B.5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES 482 B.5.2 Setting Model Parameters 482 B.5.3 Computing the Output Spectrum 484 B.5.4 SNR versus Input Amplitude Level 486 B.5.5 Parametric Analysis Considering Only One Parameter 487 B.5.6 Parametric Analysis Considering Two Parameters 488 B.5.7 Computing Histograms 489 B.6 Getting Help 489 C SIMSIDES Block Libraries and Models 491 C.1 Overview of SIMSIDES Libraries 491 C.2 Ideal Libraries 492 C.2.1 Ideal Integrators 492 C.2.1.1 Building-block Model Purpose and Description 492 C.2.1.2 Model Parameters 493 C.2.2 Ideal Resonators 493 C.2.2.1 Ideal_LD_Resonator 493 C.2.2.2 Ideal_FE_Resonator 493 C.2.2.3 Ideal_CT_Resonator 493 C.2.3 Ideal Quantizers 494 C.2.3.1 Ideal_Comparator 494 C.2.3.2 Ideal_Comparator_for_SI 495 C.2.3.3 Ideal_Multibit_Quantizer 495 C.2.3.4 Ideal_Multibit_Quantizer_for_SI 496 C.2.3.5 Ideal_Multibit_Quantizer_levels 496 C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 496 C.2.3.7 Ideal_Sampler 496 C.2.4 Ideal D/A Converters 496 C.2.4.1 Ideal_DAC_for_SI 496 C.2.4.2 Ideal_DAC_dig_level_SD2 497 C.3 Real SC Building-Block Libraries 497 C.3.1 Real SC Integrators 497 C.3.2 Real SC Resonators 501 C.4 Real SI Building-Block Libraries 503 C.4.1 Real SI Integrators 503 C.4.2 Real SI Resonators 505 C.4.3 SI Errors and Model Parameters 506 C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator 506 C.4.3.2 SI_FE(LD)_Int_Finite_Conductance 507 C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection 508 C.5 Real CT Building-Block Libraries 508 C.5.1 Real CT Integrators 508 C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks 511 C.5.1.2 Gm-MC Integrators 511 C.5.1.3 Active-RC Integrators 512 C.5.1.4 MOSFET-C Integrators 513 C.5.2 Real CT Resonators 513 C.5.2.1 Gm-C Resonators 514 C.5.2.2 Gm-LC Resonators 517 C.6 Real Quantizers & Comparators 517 C.7 Real D/A Converters 518 C.8 Auxiliary Blocks 519 Index 523
Subject Areas: Electronics & communications engineering [TJ]
