RISC System/6000 PowerPC System Architecture

9781558603448, Elsevier Science

Hardback, published 20 October 1994

320 pages
24 x 19.7 x 2.4 cm, 0.82 kg

Offers support for a wide range of products for the RISC System/6000 product line and AIX operating system, including Uni-processor (UP) and Symmetric Multiple Processor (SMP) systems. Provides important information for building many system features such as memory controllers with caches and bus-to-bus bridges. RISC System/ 6000 PowerPC System Architecture defines an architecture that allows each operating system--in particular, the AIX operating system--to run unchanged on all systems that comply with this architecture. It provides a consistent software interface across a broad range of system implementations and offers all hardware/software dependencies necessary for a successful system identification, configuration and performance tuning process.

Chapter 1 Introduction
Chapter 2 PowerPC Processor Architecture
Chapter 3 Architected system Memory Map
Chapter 4 Bring-Up and Configuration Architecture
Chapter 5 NVRAM Contents and Mapping
Chapter 6 Bus Unit Controller (BUC) Architecture
Chapter 7 IOCC Architecture
Chapter 8 System Resources
Chapter 9 External Interrupt Architecture
Chapter 10 System Exception Processing
Chapter 11 System Bus Architecture
Chapter 12 Bring-Up Function and IPLCB
Chapter 13 Vital Product Data (VPI)
Chapter 14 AIX Based Diagnostics Requirements
Appendix A Processor Dependencies
Appendix B Standard I/O Interface
Appendix C Target Market Categories
Appendix D Memory Controller Example
Appendix E System Exception Implementation Examples
Appendix F IPLCB Example
Appendix G AIX Dependencies on the IPLCB
Appendix H AIX Command and Event Indicators
Appendix I Power IOCC Arch. vs PowerPC IOCC Architecture
Appendix J 32/64 Bit BUC Arch. Differences & Considerations
Appendix K Big-Endian and Little-Endian Tutorial

Subject Areas: Computer architecture & logic design [UYF]