Microprocessor Architecture
From Simple Pipelines to Chip Multiprocessors

This book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.

Jean-Loup Baer (Author)

9780521769921, Cambridge University Press

Hardback, published 7 December 2009

382 pages, 104 b/w illus. 20 tables 117 exercises
25.7 x 18 x 2.5 cm, 0.84 kg

'The book gives a comprehensive and profound description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalers … The book is very well structured with good presentation of the material. Each chapter finishes with many exercises, examples and additional literature. All the references are very up-to-date. As a conclusion I warmly recommend this book as a textbook for a course or just as a reference book.' Zentralblatt MATH

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

1. Introduction
2. The basics
3. Superscalar processors
4. Front-end: branch prediction, instruction fetching, and register renaming
5. Back-end: instruction scheduling, memory access instructions, and clusters
6. The cache hierarchy
7. Multiprocessors
8. Multithreading and (chip) multiprocessors
9. Current limitations and future challenges.

Subject Areas: Computer hardware [UK]