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Logical Effort
Designing Fast CMOS Circuits
Ivan Sutherland (Author), Robert F. Sproull (Author), David Harris (Author)
9781558605572, Elsevier Science
Paperback / softback, published 9 February 1999
256 pages
23.4 x 19 x 1.7 cm, 0.48 kg
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes. The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
1 The Method of Logical Effort2 Design Examples3 Deriving the Method of Logical Effort4 Calculating the Logical Effort of Gates5 Calibrating the Model6 Asymmetric Logic Gates7 Unequal Rising and Falling Delays8 Circuit Families9 Forks of Amplifiers10 Branches and Interconnect11 Wide Structures12 ConclusionsA Cast of CharactersB Reference process parametersC Logical Effort ToolsD Solutions
Subject Areas: Computer architecture & logic design [UYF]
