Introduction to VLSI Design Flow

A textbook on the fundamentals of VLSI design flow, covering the various stages of design implementation, verification, and testing.

Sneh Saurabh (Author)

9781009200813, Cambridge University Press

Paperback, published 15 June 2023

800 pages
24.1 x 18.3 x 2.8 cm, 0.96 kg

Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.

Part I. Overview of VLSI Design Flow: Chapter 1. Foundation
Chapter 2. Introduction to Integrated Circuits
Chapter 3. Pre-RTL Methodologies
Chapter 4. RTL to GDS Implementation Flow
Chapter 5. Verification Techniques
Chapter 6. Testing Techniques
Chapter 7. Post-GDS Processes
Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog
Chapter 9. Simulation-based Verification
Chapter 10. RTL Synthesis
Chapter 11. Formal Verification, Chapter 12. Logic Optimization
Chapter 13. Technology Library
Chapter 14. Static Timing Analysis
Chapter 15. Constraints
Chapter 16. Technology Mapping
Chapter 17. Timing-driven Optimizations
Chapter 18. Power Analysis
Chapter 19. Power-driven Optimizations
Part III. Design for Testability (DFT): Chapter 20. Basics of DFT
Chapter 21. Scan Design
Chapter 22. Automatic Test Pattern Generation (ATPG)
Chapter 23. Built-in Self-test (BIST)
Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design
Chapter 25. Chip Planning
Chapter 26. Placement
Chapter 27. Clock Tree Synthesis (CTS)
Chapter 28. Routing
Chapter 29. Physical Verification and Signoff
Chapter 30. Post-silicon Validation.

Subject Areas: Circuits & components [TJFC]