• Formal Verification; An Essential Toolkit for Modern VLSI Design (Paperback / softback) 9780323956123
1 1
£73.59 GBP
£88.95 GBP £73.59 GBP
Sale Sold out
Free UK Shipping

Freshly Printed - allow 10 days lead

Formal Verification
An Essential Toolkit for Modern VLSI Design

A practical resource on formal verification written by industry experts

Erik Seligman (Author), Tom Schubert (Author), M. V. Achutha Kiran Kumar (Author)

9780323956123

Paperback / softback, published 26 May 2023

424 pages
23.5 x 19 x 2.7 cm, 0.88 kg

Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.

Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.

  1. Formal verification: from dreams to reality
  2. Basic formal verification algorithms
  3. Introduction to SystemVerilog Assertions
  4. Formal property verification
  5. Effective formal property verification for design exercise
  6. Effective FPV for verification
  7. Formal property verification apps for specific problems
  8. Formal equivalence verification
  9. Formal verification’s greatest bloopers: the danger of false positives
  10. Dealing with complexity
  11. Formal signoff on real projects
  12. Your new FV-aware lifestyle

Subject Areas: Computer science [UY], Computer programming / software development [UM], Microprocessors [TJFD1], Electronic devices & materials [TJFD], Circuits & components [TJFC], Electronics & communications engineering [TJ]
View full details