Designing Digital Computer Systems with Verilog

This book explains how to specify, design, and test a complete digital system using Verilog.

David J. Lilja (Author), Sachin S. Sapatnekar (Author)

9780521828666, Cambridge University Press

Hardback, published 2 December 2004

176 pages, 5 tables
25.5 x 18 x 1.8 cm, 0.53 kg

This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.

Preface
1. Controlling complexity
2. A verilogical place to start
3. Defining the instruction set architecture
4. Algorithmic behavioral modeling
5. Building an assembler for VeSPA
6. Pipelining
7. Implementation of the pipelined processor
8. Verification
Appendix A: the VeSPA instruction set architecture (ISA)
Appendix B: the VASM assembler
Index.

Subject Areas: Computer architecture & logic design [UYF], Computer hardware [UK], Electronics engineering [TJF]