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Computer Architecture
A Quantitative Approach
Features the RISC-V ("RISC Five") instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard
John L. Hennessy (Author), David A. Patterson (Author)
9780128119051, Elsevier Science
Paperback, published 15 December 2017
936 pages
23.5 x 19 x 5.6 cm, 1.79 kg
"What has made this book an enduring classic is that each edition is not an update, but an extensive revision that presents the most current information and unparalleled insight into this fascinating and fast changing field. For me, after over twenty years in this profession, it is also another opportunity to experience that student-grade admiration for two remarkable teachers." --From the Foreword by Luiz Andre Barroso, Google, Inc.
Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
Printed Text 1. Fundamentals of Quantitative Design and Analysis 2. Memory Hierarchy Design 3. Instruction-Level Parallelism and Its Exploitation 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures 5. Multiprocessors and Thread-Level Parallelism 6. The Warehouse-Scale Computer 7. Domain Specific Architectures A. Instruction Set Principles B. Review of Memory Hierarchy C. Pipelining: Basic and Intermediate Concepts Online D. Storage Systems E. Embedded Systems F. Interconnection Networks G. Vector Processors H. Hardware and Software for VLIW and EPIC I. Large-Scale Multiprocessors and Scientific Applications J. Computer Arithmetic K. Survey of Instruction Set Architectures L. Advanced Concepts on Address Translation M. Historical Perspectives and References
Subject Areas: Computer architecture & logic design [UYF]
