{"product_id":"verilog-coding-for-logic-synthesis-hardback-9780471429760","title":"Verilog Coding for Logic Synthesis (Hardback) 9780471429760","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eVerilog Coding for Logic Synthesis\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eWeng Fook Lee (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471429760, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 13 May 2003\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e336 pages, Drawings: 114 B\u0026amp;W, 0 Color; Tables: 28 B\u0026amp;W, 0 Color\u003cbr\u003e23.9 x 16.3 x 2.1 cm, 0.596 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eProvides a practical approach to Verilog design and problem solving.\u003cbr\u003e * Bulk of the book deals with practical design problems that design engineers solve on a daily basis.\u003cbr\u003e * Includes over 90 design examples.\u003cbr\u003e * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.\u003cbr\u003e * Book is suitable for use as a textbook in EE departments that have VLSI courses\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eTable of Figures.  \u003cp\u003eTable of Examples.\u003c\/p\u003e \u003cp\u003eList of Tables.\u003c\/p\u003e \u003cp\u003ePreface.\u003c\/p\u003e \u003cp\u003eAcknowledgments.\u003c\/p\u003e \u003cp\u003eTrademarks.\u003c\/p\u003e \u003cp\u003eIntroduction.\u003c\/p\u003e \u003cp\u003eAsic Design Flow.\u003c\/p\u003e \u003cp\u003eVerilog Coding.\u003c\/p\u003e \u003cp\u003eCoding Style: Best-Known Method for Synthesis.\u003c\/p\u003e \u003cp\u003eDesign Example of Programmable Timer.\u003c\/p\u003e \u003cp\u003eDesign Example of Programmable Logic Block for Peripheral Interface.\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-Interscience","offers":[{"title":"Brand New","offer_id":52293472649496,"sku":"9780471429760","price":109.19,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471429760.jpg?v=1781640924","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/verilog-coding-for-logic-synthesis-hardback-9780471429760","provider":"Freshly Printed Books","version":"1.0","type":"link"}