{"product_id":"signal-integrity-effects-in-custom-ic-and-asic-designs-hardback-9780471150428","title":"Signal Integrity Effects in Custom IC and ASIC Designs (Hardback) 9780471150428","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eSignal Integrity Effects in Custom IC and ASIC Designs\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eRaminderpal Singh (Edited by), R Singh (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471150428, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 21 December 2001\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e480 pages\u003cbr\u003e28.4 x 22.1 x 2.7 cm, 1.311 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cem\u003e\u003cfont size=\"3\"\u003e\"In the era of System-on-Chip, when large portions of the overall system are integrated on one large chip, designers are facing increasingly challenging issues. For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. System designers are given guidance in power distribution analysis, interconnect optimization, and mixed, digital-analog circuit integration challenges. Researchers and CAD engineers can get an in-depth view of the current and future requirements for full-chip CAD tools, on-chip transmission line designs, integrated passive components, and many other critical signal integrity issues. This book is bringing together a broad range of representative papers that will further the understanding both in the industrial and academic communities.\"\u003cbr\u003e (Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines)\u003cbr\u003e \u003cbr\u003e \"Electrical integrity (or environment noise) is becoming the principal obstacle in system-on-a-chip design. Digital circuits create a very noisy environment in which other digital and analog circuits must function. This environmental noise comes about because of coupling through the interconnect, power supply, and substrate. This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip.\"\u003cbr\u003e (Kenneth L. Shepard, Professor, Columbia University)\u003cbr\u003e \u003cbr\u003e \"The explosion of wireless communications that offer greater mobility and broadband communications that provide super fast access to the Internet have placed new demands on IC designers. The key to developing successful Systems on Chip designs that offer Analog and Mixed Signal capabilities is the approach used to extract and analyze the affects of parasitics on signal integrity. This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity.\"\u003cbr\u003e (Jake Buurma Senior Vice President, Worldwide Research \u0026amp; Development, Cadence Design Systems, Inc.)\u003cbr\u003e \u003cbr\u003e \"As technology scales to .1 micron and below, second order effects due to physical phenomena that were not much visible before start playing a more and more significant role. So much so that well-established methodologies and tools are not providing the necessary level of confidence to the designer that her\/his integrated circuit will perform as planned. The need for more accurate extraction and analysis is obvious when we observe horror stories about very hard to detect intermittent faults created by interactions among signals on different wires. There are two complementary approaches to the problem that come to mind as always when we go over the limit of previous methods - increase the accuracy of the analysis tools, and\/or solve the problems by imposing constraints on the degrees of freedom left to the designer. This collection of papers covers both in details. It is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection.\"\u003cbr\u003e (Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley)\u003c\/font\u003e\u003c\/em\u003e\u003c\/p\u003e\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eDieses Buch hilft Ihnen bei der Lösung spezieller Probleme beim Design von kundenspezifischen integrierten Schaltkreisen und ASICs. Behandelt werden u.a. verschiedene Einflüsse auf die Signalintegrität für hochleistungsfähige Hochfrequenzschaltungen, ASIC-Designs bei Strukturbreiten von 0,18 Mikrometern und integrierte Custom-IC-Blocks in ASIC-Designs.\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eForeword.  \u003cp\u003eFrom the Early Days of CMOS to Today.\u003c\/p\u003e \u003cp\u003eSignal Integrity: A Problem for Design and CAD Engineers.\u003c\/p\u003e \u003cp\u003ePreface.\u003c\/p\u003e \u003cp\u003eAcknowledgments.\u003c\/p\u003e \u003cp\u003eSignal Integrity Effects in Systme-on-Chip Designs - A Designer's Perspective.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 1: Interconnect Crosstalk.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eHarmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits.\u003c\/p\u003e \u003cp\u003eFastCap: A Multipole Accelerated 3-D Capacitance Extraction Program.\u003c\/p\u003e \u003cp\u003eEfficient Coupled Noise Estimation for On-Chip Interconnects.\u003c\/p\u003e \u003cp\u003eSwitching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise.\u003c\/p\u003e \u003cp\u003eDigital Sensitivity: Predicting Signal Interaction using Functional Analysis.\u003c\/p\u003e \u003cp\u003eCrosstalk Reduction for VLSI.\u003c\/p\u003e \u003cp\u003eNoise-aware Repeater Insertion and Wire Sizing For On-Chip Interconnect Hierarchical Moment-Matching.\u003c\/p\u003e \u003cp\u003ePost Global Routing Crosstalk Synthesis.\u003c\/p\u003e \u003cp\u003eMinimum Crosstalk Channel Routing.\u003c\/p\u003e \u003cp\u003eReducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design.\u003c\/p\u003e \u003cp\u003eA Postprocessing Algorithm for Crosstalk-driven Wire Perturbation.\u003c\/p\u003e \u003cp\u003eNoise in Digital Dynamic CMOS Circuits.\u003c\/p\u003e \u003cp\u003eDesign of Dynamic Circuits with Enhanced Noise Tolerance.\u003c\/p\u003e \u003cp\u003eCoupling-Driven Signal Encoding Scheme for Low-Power Interface Design.\u003c\/p\u003e \u003cp\u003eHigh Frequency Simulation and Characterization of Advanced Copper Interconnects.\u003c\/p\u003e \u003cp\u003eStatic Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-On-Insulator Technology.\u003c\/p\u003e \u003cp\u003eSynthesis of CMOS Domino Circuits for Charge Sharing Alleviation.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 2: Inductance Effects.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eOn-Chip Wiring Design Challenges for Gigahertz Operation.\u003c\/p\u003e \u003cp\u003eIC Analyses Including Extracted Inductance Models.\u003c\/p\u003e \u003cp\u003eFASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program.\u003c\/p\u003e \u003cp\u003eFull-Chip, Three-Dimensional, Shapes-Based RLC Extraction.\u003c\/p\u003e \u003cp\u003eOn-Chip Inductance Modeling and Analysis.\u003c\/p\u003e \u003cp\u003eHow to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K.\u003c\/p\u003e \u003cp\u003eFigures of Merit to Characterize the Importance of On-Chip Inductance.\u003c\/p\u003e \u003cp\u003eLayout-Techniques for Minimizing On-Chip Interconnect Self Inductance.\u003c\/p\u003e \u003cp\u003eA Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 3: Power Grid and Distribution Noise.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eFull-Chip Verification of UDSM Designs.\u003c\/p\u003e \u003cp\u003ePower Supply Noise in Future IC's: A Crystal Ball Reading.\u003c\/p\u003e \u003cp\u003eA Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs.\u003c\/p\u003e \u003cp\u003ePower Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design.\u003c\/p\u003e \u003cp\u003eAnalysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices.\u003c\/p\u003e \u003cp\u003eFull-Chip Signal Interconnect Analysis for Electromigration Reliability.\u003c\/p\u003e \u003cp\u003ePower Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits.\u003c\/p\u003e \u003cp\u003eSimulation and Optimization of the Power Distribution Network in VLSI Circuits.\u003c\/p\u003e \u003cp\u003eDesign Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC's.\u003c\/p\u003e \u003cp\u003eDesign and Analysis of Power Distribution Networks in Power PC Microprocessors.\u003c\/p\u003e \u003cp\u003eModeling the Power and Ground Effects of BGA Packages.\u003c\/p\u003e \u003cp\u003eEffects of Power\/Ground Via Distribution on the Power\/Ground Performance of C4\/BGA Packages.\u003c\/p\u003e \u003cp\u003ePower Distribution Fidelity of Wirebond Compared to Flip Chip Devices in Grid Array Packages.\u003c\/p\u003e \u003cp\u003eForming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 4: Substrate Noise.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eExperimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits.\u003c\/p\u003e \u003cp\u003ePrinciples of Substrate Crosstalk Generation in CMOS Circuits.\u003c\/p\u003e \u003cp\u003eExperimental Comparison of Substrate Noise Coupling Using Different Wafer Types.\u003c\/p\u003e \u003cp\u003eModeling and Analysis of Substrate Coupling in Integrated Circuits.\u003c\/p\u003e \u003cp\u003eFast Methods for Extraction and Sparsification of Substrate Coupling.\u003c\/p\u003e \u003cp\u003eSUBWAVE: A Methodology for Modeling Digital Substrate Noise Injection in Mixed-Signal ICs.\u003c\/p\u003e \u003cp\u003eSubstrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD\/Latchup Circuit Simulation.\u003c\/p\u003e \u003cp\u003eAnalysis of Ground-Bounce Induced Substrate Noise Coupling in a Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise Effects on a Mixed-Signal Chip.\u003c\/p\u003e \u003cp\u003eA Methodology for Measurement and Characterization of Substrate Noise in High Frequency Circuits.\u003c\/p\u003e \u003cp\u003eMeasurement of Digital Noise in Mixed-Signal Integrated Circuits.\u003c\/p\u003e \u003cp\u003eEffects of Substrate Resistances on LNA Performance and a Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology.\u003c\/p\u003e \u003cp\u003eA Study of Oscillator Jitter Due to Supply and Substrate Noise.\u003c\/p\u003e \u003cp\u003eCMOS Technology Characterization for Analog and RF Design.\u003c\/p\u003e \u003cp\u003eNoise Reduction Is Crucial to Mixed-Signal ASIC Design Success (Parts I \u0026amp; II).\u003c\/p\u003e \u003cp\u003eAuthor Index.\u003c\/p\u003e \u003cp\u003eSubject Index.\u003c\/p\u003e \u003cp\u003eAbout the Editor.\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52286231839000,"sku":"9780471150428","price":144.19,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471150428.jpg?v=1781547282","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/signal-integrity-effects-in-custom-ic-and-asic-designs-hardback-9780471150428","provider":"Freshly Printed Books","version":"1.0","type":"link"}