{"product_id":"practical-esd-protection-design-hardback-9781119850403","title":"Practical ESD Protection Design (Hardback) 9781119850403","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003ePractical ESD Protection Design\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eAlbert Wang (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781119850403, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 17 December 2021\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e432 pages\u003cbr\u003e1 x 1 x 1 cm, 0.454 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eAn authoritative single-volume reference on the design and analysis of ESD protection for ICs\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eElectrostatic discharge (ESD) is a major reliability challenge to semiconductors, integrated circuits (ICs), and microelectronic systems. On-chip ESD protection is a vital to any electronic products, such as smartphones, laptops, tablets, and other electronic devices. \u003ci\u003ePractical ESD Protection Design\u003c\/i\u003e provides comprehensive and systematic guidance on all major aspects of designs of on-chip ESD protection for integrated circuits (ICs).\u003c\/p\u003e \u003cp\u003eWritten for students and practicing engineers alike, this one-stop resource covers essential theories, hands-on design skills, computer-aided design (CAD) methods, characterization and analysis techniques, and more on ESD protection designs. Detailed chapters examine an array of topics ranging from fundamental to advanced, including ESD phenomena, ESD failure analysis, ESD testing models, ESD protection devices and circuits, ESD design layout and technology effects, ESD design flows and co-design methods, ESD modelling and CAD techniques, and future ESD protection concepts. Based on the author’s decades of design,  research and teaching experiences, \u003ci\u003ePractical ESD Protection Design\u003c\/i\u003e:\u003c\/p\u003e \u003cp\u003e• Features numerous real-world ESD protection design examples\u003c\/p\u003e \u003cp\u003e• Emphasizes on ESD protection design techniques and procedures\u003c\/p\u003e \u003cp\u003e• Describes ESD-IC co-design methodology for high-performance mixed-signal ICs and broadband radio-frequency (RF) ICs\u003c\/p\u003e \u003cp\u003e• Discusses CAD-based ESD protection design optimization and prediction using both Technology and Electrical Computer-Aided Design (TCAD\/ECAD) simulation\u003c\/p\u003e \u003cp\u003e• Addresses new ESD CAD algorithms and tools for full-chip ESD physical design verification\u003c\/p\u003e \u003cp\u003e• Explores the disruptive future outlook of ESD protection\u003c\/p\u003e \u003cp\u003e\u003ci\u003ePractical ESD Protection Design\u003c\/i\u003e is a valuable reference for industrial engineers and academic researchers in the field, and an excellent textbook for electronic engineering courses in semiconductor microelectronics and integrated circuit designs.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eAuthor Biography xi\u003c\/p\u003e \u003cp\u003ePreface xiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Why ESD? 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 A Historical Perspective 1\u003c\/p\u003e \u003cp\u003e1.2 ESD and the Dangers 3\u003c\/p\u003e \u003cp\u003e1.3 ESD Protection: The Principles 9\u003c\/p\u003e \u003cp\u003e1.4 ESD Protection: More or Less? 13\u003c\/p\u003e \u003cp\u003e1.5 ESD Protection: Evolution to Revolution 15\u003c\/p\u003e \u003cp\u003eReferences 15\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 ESD Failure Analysis 19\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 ESD Failure Analysis 19\u003c\/p\u003e \u003cp\u003e2.1.1 ESD Failure Criteria 19\u003c\/p\u003e \u003cp\u003e2.1.2 Hard and Soft ESD Failures 20\u003c\/p\u003e \u003cp\u003e2.2 ESD FA Techniques 20\u003c\/p\u003e \u003cp\u003e2.3 ESD Failure Signatures 22\u003c\/p\u003e \u003cp\u003e2.4 ESD Soft Failures 38\u003c\/p\u003e \u003cp\u003e2.5 ESD Failure Correlation 41\u003c\/p\u003e \u003cp\u003e2.6 ESD Failure Models 44\u003c\/p\u003e \u003cp\u003eReferences 47\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 ESD Test Models and Standards 51\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 ESD Origins 51\u003c\/p\u003e \u003cp\u003e3.2 HBM Model 52\u003c\/p\u003e \u003cp\u003e3.3 mm Model 58\u003c\/p\u003e \u003cp\u003e3.4 CDM Model 61\u003c\/p\u003e \u003cp\u003e3.5 IEC Model 67\u003c\/p\u003e \u003cp\u003e3.6 TLP Model 69\u003c\/p\u003e \u003cp\u003e3.7 Summary 74\u003c\/p\u003e \u003cp\u003eReferences 75\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 ESD Protection Devices 77\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 On-Chip ESD Protection Mechanisms 77\u003c\/p\u003e \u003cp\u003e4.1.1 Switch for ESD Discharge 77\u003c\/p\u003e \u003cp\u003e4.1.2 ESD Protection: Active versus Passive 81\u003c\/p\u003e \u003cp\u003e4.2 Diode for ESD Protection 84\u003c\/p\u003e \u003cp\u003e4.2.1 Diode Device Physics 84\u003c\/p\u003e \u003cp\u003e4.2.2 Diode in ESD Protection 85\u003c\/p\u003e \u003cp\u003e4.2.3 Diode ESD Parasitic Modeling 87\u003c\/p\u003e \u003cp\u003e4.3 BJT for ESD Protection 87\u003c\/p\u003e \u003cp\u003e4.3.1 BJT Device Physics 88\u003c\/p\u003e \u003cp\u003e4.3.2 BJT in ESD Protection 90\u003c\/p\u003e \u003cp\u003e4.3.3 BJT ESD Parasitic Modeling 92\u003c\/p\u003e \u003cp\u003e4.4 MOSFET for ESD Protection 93\u003c\/p\u003e \u003cp\u003e4.4.1 MOSFET Device Physics 94\u003c\/p\u003e \u003cp\u003e4.4.2 ggMOS in ESD Protection 95\u003c\/p\u003e \u003cp\u003e4.4.3 MOSFET ESD Parasitic Modeling 98\u003c\/p\u003e \u003cp\u003e4.5 SCR for ESD Protection 99\u003c\/p\u003e \u003cp\u003e4.5.1 SCR Device Physics 100\u003c\/p\u003e \u003cp\u003e4.5.2 SCR in ESD Protection 102\u003c\/p\u003e \u003cp\u003e4.5.3 SCR ESD Parasitic Modeling 106\u003c\/p\u003e \u003cp\u003e4.6 Summary 107\u003c\/p\u003e \u003cp\u003eReferences 109\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 ESD Protection Circuits 111\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 I\/O ESD Protection 111\u003c\/p\u003e \u003cp\u003e5.1.1 Two-Stage ESD Protection 112\u003c\/p\u003e \u003cp\u003e5.1.2 Multiple-Fingers ESD Protection 113\u003c\/p\u003e \u003cp\u003e5.1.3 MOSFET ESD Protection Circuits 114\u003c\/p\u003e \u003cp\u003e5.1.4 BJT ESD Protection Circuits 117\u003c\/p\u003e \u003cp\u003e5.1.5 SCR ESD Protection Circuits 120\u003c\/p\u003e \u003cp\u003e5.2 ESD Self-Protection 121\u003c\/p\u003e \u003cp\u003e5.2.1 Output ESD Protection 121\u003c\/p\u003e \u003cp\u003e5.2.2 ESD Self-Protection 124\u003c\/p\u003e \u003cp\u003e5.3 Low-Triggering ESD Protection Circuits 124\u003c\/p\u003e \u003cp\u003e5.4 ESD Power Clamps 129\u003c\/p\u003e \u003cp\u003e5.4.1 Diode-String Power Clamps 131\u003c\/p\u003e \u003cp\u003e5.4.2 MOSFET Power Clamps 134\u003c\/p\u003e \u003cp\u003e5.4.3 SCR Power Clamps 135\u003c\/p\u003e \u003cp\u003e5.4.4 Any Switch Power Clamps 135\u003c\/p\u003e \u003cp\u003e5.5 Summary 136\u003c\/p\u003e \u003cp\u003eReferences 137\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Full-Chip ESD Protection 139\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Full-Chip ESD Protection Principles 139\u003c\/p\u003e \u003cp\u003e6.2 ESD Protection Design Window 140\u003c\/p\u003e \u003cp\u003e6.3 Advanced ESD Protection: More at Less 142\u003c\/p\u003e \u003cp\u003e6.3.1 Dual-Polarity ESD Protection 143\u003c\/p\u003e \u003cp\u003e6.3.2 Multiple-Polarity ESD Protection 147\u003c\/p\u003e \u003cp\u003e6.4 Full-Chip ESD Protection Schemes 150\u003c\/p\u003e \u003cp\u003e6.4.1 Full-Chip ESD Consideration 150\u003c\/p\u003e \u003cp\u003e6.4.2 Pad-Clamp Scheme 151\u003c\/p\u003e \u003cp\u003e6.4.3 Global ESD Bus Scheme 153\u003c\/p\u003e \u003cp\u003e6.5 No Universal ESD Protection Solution 154\u003c\/p\u003e \u003cp\u003eReferences 155\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Mixed-Signal and HV ESD Protection 157\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 ESD Protection for Mixed-Signal ICs 157\u003c\/p\u003e \u003cp\u003e7.2 ESD Protection for Multiple-Voltages ICs 162\u003c\/p\u003e \u003cp\u003e7.3 ESD Protection for High-Voltage ICs 167\u003c\/p\u003e \u003cp\u003e7.3.1 ESD Design Window Compliance 167\u003c\/p\u003e \u003cp\u003e7.3.2 Latch-up Immunity 173\u003c\/p\u003e \u003cp\u003e7.4 Summary 174\u003c\/p\u003e \u003cp\u003eReferences 175\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 TCAD-Based Mixed-Mode ESD Protection Designs 177\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 ESD Design Optimization and Prediction 177\u003c\/p\u003e \u003cp\u003e8.2 TCAD-Based Mixed-Mode ESD Simulation-Design Methodology 182\u003c\/p\u003e \u003cp\u003e8.3 Mixed-Mode ESD Simulation-Design Examples 188\u003c\/p\u003e \u003cp\u003e8.3.1 Example 1: Understand TCAD ESD Simulation 188\u003c\/p\u003e \u003cp\u003e8.3.2 Example-2: ggNMOS versus gcNMOS ESD Protection 192\u003c\/p\u003e \u003cp\u003e8.3.3 Example-3: ESD Power Clamp in 0.35 μmCMOS 196\u003c\/p\u003e \u003cp\u003e8.3.4 Example-4: Optimize HV ESD Protection Design 199\u003c\/p\u003e \u003cp\u003e8.3.5 Example-5: ESD Layout Analysis by 3D TCAD 203\u003c\/p\u003e \u003cp\u003e8.3.6 Example-6: Multiple-Stimuli TCAD ESD Simulation 210\u003c\/p\u003e \u003cp\u003e8.4 Summary 218\u003c\/p\u003e \u003cp\u003eReferences 219\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 RF ESD Protection 221\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 What Is Special for RF ESD Protection? 221\u003c\/p\u003e \u003cp\u003e9.2 RF ESD Protection Characterization 226\u003c\/p\u003e \u003cp\u003e9.3 Low-Parasitic ESD Protection Solutions 232\u003c\/p\u003e \u003cp\u003e9.4 RF ESD Protection Design Example 233\u003c\/p\u003e \u003cp\u003e9.5 Summary 236\u003c\/p\u003e \u003cp\u003eReferences 237\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 ESD-RFIC Co-Design 239\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 ESD-IC Interactions 239\u003c\/p\u003e \u003cp\u003e10.1.1 IC Affects ESD Protection 239\u003c\/p\u003e \u003cp\u003e10.1.2 ESD Affects IC Performance 241\u003c\/p\u003e \u003cp\u003e10.2 ESD-RFIC Co-Design 248\u003c\/p\u003e \u003cp\u003e10.2.1 ESD-RFIC Co-Design Principle 249\u003c\/p\u003e \u003cp\u003e10.2.2 ESD–RFIC Co-Design Examples 251\u003c\/p\u003e \u003cp\u003e10.3 Summary 259\u003c\/p\u003e \u003cp\u003eReferences 259\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 ESD Layout Designs 261\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Layout is Critical to ESD Protection 261\u003c\/p\u003e \u003cp\u003e11.2 Basic ESD Protection Layout 262\u003c\/p\u003e \u003cp\u003e11.3 Advanced ESD Protection Layout 274\u003c\/p\u003e \u003cp\u003e11.3.1 Advanced ESD Layout Considerations 274\u003c\/p\u003e \u003cp\u003e11.3.2 ESD Design Layout is an Art 278\u003c\/p\u003e \u003cp\u003e11.4 3D TCAD for ESD Layout Designs 284\u003c\/p\u003e \u003cp\u003e11.5 Summary 294\u003c\/p\u003e \u003cp\u003eReferences 295\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 ESD versus IC Technologies 297\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 IC Technologies and ESD Protection 297\u003c\/p\u003e \u003cp\u003e12.1.1 ESD Metal Interconnects 297\u003c\/p\u003e \u003cp\u003e12.1.2 Technology-ESD Co-Development 299\u003c\/p\u003e \u003cp\u003e12.1.3 Graphene Heat Spreading 305\u003c\/p\u003e \u003cp\u003e12.2 Technology Affects ESD Design Window 305\u003c\/p\u003e \u003cp\u003e12.3 Lowering ESD Protection for Advanced ICs? 306\u003c\/p\u003e \u003cp\u003e12.4 Summary 308\u003c\/p\u003e \u003cp\u003eReferences 308\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 ESD Circuit Simulation by SPICE 311\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 ESD Device Behavior Modeling 311\u003c\/p\u003e \u003cp\u003e13.2 Full-Chip ESD Circuit Simulation by SPICE 314\u003c\/p\u003e \u003cp\u003e13.2.1 Principle for ESD Circuit Simulation by SPICE 314\u003c\/p\u003e \u003cp\u003e13.2.2 Circuit-Level ESD Design Verification by SPICE 319\u003c\/p\u003e \u003cp\u003e13.3 Summary 326\u003c\/p\u003e \u003cp\u003eReferences 326\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Emerging ESD Protection 327\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Emerging ESD Protection Challenges 327\u003c\/p\u003e \u003cp\u003e14.2 Dispensable ESD Protection 328\u003c\/p\u003e \u003cp\u003e14.3 Field-Programmable ESD Protection 332\u003c\/p\u003e \u003cp\u003e14.3.1 Nano-Crystal Quantum-Dots ESD Protection 332\u003c\/p\u003e \u003cp\u003e14.3.2 SONOS ESD Protection 334\u003c\/p\u003e \u003cp\u003e14.4 Interposer\/TSV-Based ESD Protection 337\u003c\/p\u003e \u003cp\u003e14.5 Summary 341\u003c\/p\u003e \u003cp\u003eReferences 342\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 ESD CAD for Full-Chip Design Verification 345\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Full-Chip ESD Design Verification 345\u003c\/p\u003e \u003cp\u003e15.2 CAD Algorithms for ESD Design Verification 347\u003c\/p\u003e \u003cp\u003e15.3 Full-Chip ESD Design Verification Examples 353\u003c\/p\u003e \u003cp\u003e15.4 Summary 363\u003c\/p\u003e \u003cp\u003eReferences 364\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 New CDM ESD Protection 367\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Misconception in CDM ESD Protection 367\u003c\/p\u003e \u003cp\u003e16.2 Analyzing Pad-Based CDM ESD Protection 370\u003c\/p\u003e \u003cp\u003e16.3 Internally Distributed CDM ESD Protection 385\u003c\/p\u003e \u003cp\u003e16.4 Summary 391\u003c\/p\u003e \u003cp\u003eReferences 392\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 Future ESD Protection Outlook 395\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 The Fundamental ESD Protection Problem 395\u003c\/p\u003e \u003cp\u003e17.2 Above-IC Nano-Crossbar Array ESD Switch 396\u003c\/p\u003e \u003cp\u003e17.3 Graphene ESD Protection Switch 401\u003c\/p\u003e \u003cp\u003e17.4 Graphene ESD Protection Interconnects 405\u003c\/p\u003e \u003cp\u003e17.5 Future ESD Protection Outlook 407\u003c\/p\u003e \u003cp\u003e17.6 Summary 410\u003c\/p\u003e \u003cp\u003eReferences 411\u003c\/p\u003e \u003cp\u003eIndex 413\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52430977237272,"sku":"9781119850403","price":97.69,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781119850403.jpg?v=1784767191","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/practical-esd-protection-design-hardback-9781119850403","provider":"Freshly Printed Books","version":"1.0","type":"link"}