{"product_id":"power-systems-on-chip-practical-aspects-of-design-hardback-9781786300812","title":"Power Systems-On-Chip; Practical Aspects of Design (Hardback) 9781786300812","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003ePower Systems-On-Chip\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003ePractical Aspects of Design\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eBruno Allard (Edited by), Allard (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781786300812, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 5 December 2016\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e352 pages\u003cbr\u003e23.6 x 16.3 x 2.3 cm, 0.68 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eThe book gathers the major issues involved in the practical design of Power Management solutions in wireless products as Internet-of-things. Presentation is not about state-of-the-art but about appropriation of validated recent technologies by practicing engineers. The book delivers insights on major trade-offs and a presentation of examples as a cookbook. The content is segmented in chapters to make access easier for the lay-person.\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003ePreface xi\u003c\/p\u003e \u003cp\u003eIntroduction  xv\u003cbr\u003e\u003ci\u003eBruno ALLARD\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1. Control Strategies and CAD Approach 1\u003c\/b\u003e\u003cbr\u003e\u003ci\u003ePedro ALOU, José A. COBOS, Jesus A. OLIVER, Bruno ALLARD, Benôit LABBE, Aleksandar PRODIC and Aleksandar RADIC\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1. Objectives 2\u003c\/p\u003e \u003cp\u003e1.2. Operation principle of three non-isolated converters  8\u003c\/p\u003e \u003cp\u003e1.2.1. Buck converter operation 8\u003c\/p\u003e \u003cp\u003e1.2.2. Boost converter operation 10\u003c\/p\u003e \u003cp\u003e1.2.3. Buck-boost converter operation 11\u003c\/p\u003e \u003cp\u003e1.3. Power stage 13\u003c\/p\u003e \u003cp\u003e1.3.1. MOSFET switching an inductive load  13\u003c\/p\u003e \u003cp\u003e1.3.2. Extracting the parasitic capacitance values using simulations  18\u003c\/p\u003e \u003cp\u003e1.3.3. Power-stage design issues 19\u003c\/p\u003e \u003cp\u003e1.3.4. Segmented power stage and multiphase operation 21\u003c\/p\u003e \u003cp\u003e1.3.5. LC filter design space 22\u003c\/p\u003e \u003cp\u003e1.4. Control stage  29\u003c\/p\u003e \u003cp\u003e1.4.1. Voltage-mode control of the buck converter  29\u003c\/p\u003e \u003cp\u003e1.4.2. The RHP zero of the boost converter  35\u003c\/p\u003e \u003cp\u003e1.4.3. Current-mode control 37\u003c\/p\u003e \u003cp\u003e1.4.4. Hysteretic and sliding-mode control 40\u003c\/p\u003e \u003cp\u003e1.4.5. Ripple-based controls for fast dynamics 45\u003c\/p\u003e \u003cp\u003e1.4.6. V1 concept: description and applicability  52\u003c\/p\u003e \u003cp\u003e1.4.7. Overview of the synchronization of asynchronous modulations  59\u003c\/p\u003e \u003cp\u003e1.4.8. PFM - pulse skipping: burst modes 62\u003c\/p\u003e \u003cp\u003e1.5. Minimum voltage deviation controller  63\u003c\/p\u003e \u003cp\u003e1.5.1. Introduction  64\u003c\/p\u003e \u003cp\u003e1.5.2. Integrated circuit implementation and experimental results 67\u003c\/p\u003e \u003cp\u003e1.6. CAD tools for PwrSoC design and optimization  69\u003c\/p\u003e \u003cp\u003e1.6.1. Overview of the CAD requirements 71\u003c\/p\u003e \u003cp\u003e1.6.2. Loss models for integrated inductors and semiconductors  73\u003c\/p\u003e \u003cp\u003e1.6.3. Optimization algorithms 82\u003c\/p\u003e \u003cp\u003e1.6.4. Outcome of the optimization (topology, area, loss, fsw, detailed design) 84\u003c\/p\u003e \u003cp\u003e1.6.5. Impact of technology 87\u003c\/p\u003e \u003cp\u003e1.7. Conclusion 91\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2. Magnetic Components for Increased Power Density 93\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eSantosh KULKARNI and Cian O’MATHUNA\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1. Commercial and research trends towards PwrSiP and PwrSoC  96\u003c\/p\u003e \u003cp\u003e2.2. Review of magnetics 104\u003c\/p\u003e \u003cp\u003e2.2.1. Micro-inductor structures 104\u003c\/p\u003e \u003cp\u003e2.2.2. Magnetic materials and processing for thin film integrated micro-magnetic devices 111\u003c\/p\u003e \u003cp\u003e2.3. Figures of merit for performance of integrated magnetics  118\u003c\/p\u003e \u003cp\u003e2.3.1. Figure of merit – DC performance  118\u003c\/p\u003e \u003cp\u003e2.3.2. Figure of merit and AC performance  123\u003c\/p\u003e \u003cp\u003e2.4. Technology roadmap and challenges 123\u003c\/p\u003e \u003cp\u003e2.4.1. Market drivers 124\u003c\/p\u003e \u003cp\u003e2.4.2. PwrSoC supply chain challenges 126\u003c\/p\u003e \u003cp\u003e2.4.3. PwrSoC technology platform 127\u003c\/p\u003e \u003cp\u003e2.4.4. Integrated magnetic devices for PwrSoC – opportunities 128\u003c\/p\u003e \u003cp\u003e2.5. Conclusions  130\u003c\/p\u003e \u003cp\u003e2.6. Acknowledgments 132\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3. Dielectric Components for Increased Power Density 133\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eFrédéric VOIRON\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1. Introduction  133\u003c\/p\u003e \u003cp\u003e3.2. Basics of dielectric physics  135\u003c\/p\u003e \u003cp\u003e3.2.1. Forewords 135\u003c\/p\u003e \u003cp\u003e3.2.2. Polarization, dipole and capacitance 135\u003c\/p\u003e \u003cp\u003e3.2.3. Polarization mechanisms in dielectrics 136\u003c\/p\u003e \u003cp\u003e3.2.4. Losses in dielectrics  139\u003c\/p\u003e \u003cp\u003e3.3. Silicon integrated capacitors 140\u003c\/p\u003e \u003cp\u003e3.3.1. Integrated capacitors for enhanced performance  141\u003c\/p\u003e \u003cp\u003e3.4. Integrated capacitors for enhanced reliability  145\u003c\/p\u003e \u003cp\u003e3.4.1. Dielectric processing 145\u003c\/p\u003e \u003cp\u003e3.4.2. Lifetime considerations  149\u003c\/p\u003e \u003cp\u003e3.5. Integrated capacitor optimization for power switching 150\u003c\/p\u003e \u003cp\u003e3.5.1. Regular layout 150\u003c\/p\u003e \u003cp\u003e3.5.2. Broad band modeling 150\u003c\/p\u003e \u003cp\u003e3.5.3. Capacitance parasitic suppression  153\u003c\/p\u003e \u003cp\u003e3.6. Conclusion 154\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4. On-board Power Management DC\/DC Inductive Converter  157\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eBenoît LABBE and Bruno ALLARD\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1. Specifications 157\u003c\/p\u003e \u003cp\u003e4.1.1. Load-related requirements  158\u003c\/p\u003e \u003cp\u003e4.1.2. System-related requirements 159\u003c\/p\u003e \u003cp\u003e4.1.3. Power delivery network  161\u003c\/p\u003e \u003cp\u003e4.2. Current-mode sliding-mode control implementation  161\u003c\/p\u003e \u003cp\u003e4.2.1. System analysis: voltage regulation loops  162\u003c\/p\u003e \u003cp\u003e4.2.2. System analysis: loop delay control 167\u003c\/p\u003e \u003cp\u003e4.2.3. System analysis: switching frequency control 168\u003c\/p\u003e \u003cp\u003e4.2.4. Design 169\u003c\/p\u003e \u003cp\u003e4.2.5. Results 172\u003c\/p\u003e \u003cp\u003e4.3. Conclusions . 174\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5. On-Chip Power Management DC\/DC Switched-Capacitor Converter  179\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eGael PILLONNET, Thomas SOUVIGNET and Bruno ALLARD\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1. Topology description 180\u003c\/p\u003e \u003cp\u003e5.1.1. Ratio calculation  180\u003c\/p\u003e \u003cp\u003e5.1.2. Basic scheme  182\u003c\/p\u003e \u003cp\u003e5.1.3. Steady-state modeling 183\u003c\/p\u003e \u003cp\u003e5.2. Pros and cons  190\u003c\/p\u003e \u003cp\u003e5.2.1. Key advantages  190\u003c\/p\u003e \u003cp\u003e5.2.2. Main disadvantages  192\u003c\/p\u003e \u003cp\u003e5.3. State-of-the-art 193\u003c\/p\u003e \u003cp\u003e5.3.1. Research scope and main focus 194\u003c\/p\u003e \u003cp\u003e5.3.2. Integration level  194\u003c\/p\u003e \u003cp\u003e5.3.3. The point-of-load (POL) application  195\u003c\/p\u003e \u003cp\u003e5.4. Design example  204\u003c\/p\u003e \u003cp\u003e5.4.1. Landscape of demonstrated solutions  204\u003c\/p\u003e \u003cp\u003e5.4.2. Selected architecture 207\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6. High-Switching Frequency Inductive DC\/DC Converters  213\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eChristian MARTIN, Florian NEVEU and Bruno ALLARD\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1. Context and topologies  214\u003c\/p\u003e \u003cp\u003e6.1.1. Discussion on figures of merit  219\u003c\/p\u003e \u003cp\u003e6.1.2. Outstanding state-of-the-art performances 224\u003c\/p\u003e \u003cp\u003e6.2. Cascode power stage 225\u003c\/p\u003e \u003cp\u003e6.3. High-quality decoupling 229\u003c\/p\u003e \u003cp\u003e6.4. Design considerations for passive components 232\u003c\/p\u003e \u003cp\u003e6.5. Integrated inductor characterization 235\u003c\/p\u003e \u003cp\u003e6.5.1. Harmonic characterization  235\u003c\/p\u003e \u003cp\u003e6.5.2. Time-domain characterization  237\u003c\/p\u003e \u003cp\u003e6.5.3. Converter experimental characterization  242\u003c\/p\u003e \u003cp\u003e6.6. Conclusion 246\u003c\/p\u003e \u003cp\u003e6.7. Acknowledgments 247\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7. Hybrid and Multi-level Converter Topologies for On-Chip Implementation of Reduced Voltage-Swing Converters 249\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eAleksandar PRODIC, Sheikh Mohammad AHSANUZZAMAN, Behzad MAHDAVIKHAH and Timothy MCRAE\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1. Introduction  249\u003c\/p\u003e \u003cp\u003e7.1.1. Inductor volume reduction through voltage swing minimization  251\u003c\/p\u003e \u003cp\u003e7.2. Cascaded hybrid SC-inductive topologies  254\u003c\/p\u003e \u003cp\u003e7.2.1. Merged switched-capacitor multi-phase buck (MSCB) converter  255\u003c\/p\u003e \u003cp\u003e7.3. Hybrid serial input\/output converters  262\u003c\/p\u003e \u003cp\u003e7.3.1. HSI\/O power processing efficiency and power division 265\u003c\/p\u003e \u003cp\u003e7.3.2. Switched-capacitor conversion ratio 267\u003c\/p\u003e \u003cp\u003e7.3.3. Passive volume and switch voltage stress  269\u003c\/p\u003e \u003cp\u003e7.4. An on-chip integrated high-density power management solution for portable applications based on a multi-output switched-capacitor circuit 270\u003c\/p\u003e \u003cp\u003e7.5. Multi-level and flying capacitor multi-level converters  279\u003c\/p\u003e \u003cp\u003e7.6. Conclusion 282\u003c\/p\u003e \u003cp\u003eBibliography 285\u003c\/p\u003e \u003cp\u003eList of Acronyms  311\u003c\/p\u003e \u003cp\u003eList of Authors  315\u003c\/p\u003e \u003cp\u003eIndex  317\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-ISTE","offers":[{"title":"Brand New","offer_id":52446340808984,"sku":"9781786300812","price":100.57,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781786300812.jpg?v=1785111354","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/power-systems-on-chip-practical-aspects-of-design-hardback-9781786300812","provider":"Freshly Printed Books","version":"1.0","type":"link"}