{"product_id":"nonvolatile-memory-technologies-with-emphasis-on-flash-a-comprehensive-guide-to-understanding-and-using-flash-memory-devices-hardback-9780471770022","title":"Nonvolatile Memory Technologies with Emphasis on Flash; A Comprehensive Guide to Understanding and Using Flash Memory Devices (Hardback) 9780471770022","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eNonvolatile Memory Technologies with Emphasis on Flash\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eA Comprehensive Guide to Understanding and Using Flash Memory Devices\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eJoe Brewer (Edited by), JE Brewer (Author), Manzur Gill (Edited by)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471770022, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 1 February 2008\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e792 pages, Photos: 25 B\u0026amp;W, 0 Color; Drawings: 670 B\u0026amp;W, 0 Color\u003cbr\u003e26.2 x 18.7 x 4.1 cm, 1.497 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003ePresented here is an all-inclusive treatment of Flash technology, including Flash memory chips, Flash embedded in logic, binary cell Flash, and multilevel cell Flash. The book begins with a tutorial of elementary concepts to orient readers who are less familiar with the subject. Next, it covers all aspects and variations of Flash technology at a mature engineering level: basic device structures, principles of operation, related process technologies, circuit design, overall design tradeoffs, device testing, reliability, and applications.\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cb\u003eForeword.\u003c\/b\u003e  \u003cp\u003e\u003cb\u003ePreface.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eContributors.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1\u003c\/b\u003e \u003cb\u003eINTRODUCTION TO NONVOLATILE MEMORY\u003c\/b\u003e (\u003ci\u003eJoe E. Brewer\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e1.1 Introduction.\u003c\/p\u003e \u003cp\u003e1.2 Elementary Memory Concepts.\u003c\/p\u003e \u003cp\u003e1.3 Unique Aspects of Nonvolatile Memory.\u003c\/p\u003e \u003cp\u003e1.4 Flash Memory and Flash Cell Variations.\u003c\/p\u003e \u003cp\u003e1.5 Semiconductor Device Technology Generations.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2\u003c\/b\u003e \u003cb\u003eFLASH MEMORY APPLICATIONS\u003c\/b\u003e (\u003ci\u003eGary Forni, Collin Ong, Christine Rice, Ken McKee, and Ronald J. Bauer\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e2.1 Introduction.\u003c\/p\u003e \u003cp\u003e2.2 Code Storage.\u003c\/p\u003e \u003cp\u003e2.3 Data Storage.\u003c\/p\u003e \u003cp\u003e2.4 Code+Data Storage.\u003c\/p\u003e \u003cp\u003e2.5 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3\u003c\/b\u003e \u003cb\u003eMEMORY CIRCUIT TECHNOLOGIES\u003c\/b\u003e (\u003ci\u003eGiulio G. Marotta, Giovanni Naso, and Giuseppe Savarese\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e3.1 Introduction.\u003c\/p\u003e \u003cp\u003e3.2 Flash Cell Basic Operation.\u003c\/p\u003e \u003cp\u003e3.3 Flash Memory Architecture.\u003c\/p\u003e \u003cp\u003e3.4 Redundancy.\u003c\/p\u003e \u003cp\u003e3.5 Error Correction Coding (ECC).\u003c\/p\u003e \u003cp\u003e3.6 Design for Testability (DFT).\u003c\/p\u003e \u003cp\u003e3.7 Flash-Specifi c Circuit Techniques.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4\u003c\/b\u003e \u003cb\u003ePHYSICS OF FLASH MEMORIES\u003c\/b\u003e  (\u003ci\u003eJ. Van Houdt, R. Degraeve, G. Groeseneken, and H. E. Maes\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e4.1 Introduction.\u003c\/p\u003e \u003cp\u003e4.2 Basic Operating Principles and Memory Characteristics.\u003c\/p\u003e \u003cp\u003e4.3 Physics of Programming and Erase Mechanisms.\u003c\/p\u003e \u003cp\u003e4.4 Physics of Degradation and Disturb Mechanisms.\u003c\/p\u003e \u003cp\u003e4.5 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5\u003c\/b\u003e \u003cb\u003eNOR FLASH STACKED AND SPLIT-GATE MEMORY TECHNOLOGY\u003c\/b\u003e (\u003ci\u003eStephen N. Keeney, Manzur Gill, and David Sweetman\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e5.1 Introduction.\u003c\/p\u003e \u003cp\u003e5.2 ETOX Flash Cell Technology.\u003c\/p\u003e \u003cp\u003e5.3 SST SuperFlash EEPROM Cell Technology.\u003c\/p\u003e \u003cp\u003e5.4 Reliability Issues and Solutions.\u003c\/p\u003e \u003cp\u003e5.5 Applications.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 NAND FLASH MEMORY TECHNOLOGY\u003c\/b\u003e (\u003ci\u003eKoji Sakui and Kang-Deog Suh\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e6.1 Overview of NAND EEPROM.\u003c\/p\u003e \u003cp\u003e6.2 NAND Cell Operation.\u003c\/p\u003e \u003cp\u003e6.3 NAND Array Architecture and Operation.\u003c\/p\u003e \u003cp\u003e6.4 Program Threshold Control and Program \u003ci\u003eVt\u003c\/i\u003e Spread Reduction.\u003c\/p\u003e \u003cp\u003e6.5 Process and Scaling Issues.\u003c\/p\u003e \u003cp\u003e6.6 Key Circuits and Circuit\/Technology Interactions.\u003c\/p\u003e \u003cp\u003e6.7 Multilevel NAND.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7\u003c\/b\u003e \u003cb\u003eDINOR FLASH MEMORY TECHNOLOGY\u003c\/b\u003e (\u003ci\u003eMoriyoshi Nakashima and Natsuo Ajika\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e7.1 Introduction.\u003c\/p\u003e \u003cp\u003e7.2 DINOR Operation and Array Architecture.\u003c\/p\u003e \u003cp\u003e7.3 DINOR Technology Features.\u003c\/p\u003e \u003cp\u003e7.4 DINOR Circuit for Low-Voltage Operation.\u003c\/p\u003e \u003cp\u003e7.5 Background Operation Function.\u003c\/p\u003e \u003cp\u003e7.6 P-Channel DINOR Architecture.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8\u003c\/b\u003e \u003cb\u003eP-CHANNEL FLASH MEMORY TECHNOLOGY\u003c\/b\u003e (\u003ci\u003eFrank Ruei-Ling Lin and Charles Ching-Hsiang Hsu\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e8.1 Introduction.\u003c\/p\u003e \u003cp\u003e8.2 Device Structure.\u003c\/p\u003e \u003cp\u003e8.3 Operations of P-Channel Flash.\u003c\/p\u003e \u003cp\u003e8.4 Array Architecture of P-Channel Flash.\u003c\/p\u003e \u003cp\u003e8.5 Evolution of P-Channel Flash.\u003c\/p\u003e \u003cp\u003e8.6 Processing Technology for P-Channel Flash.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9\u003c\/b\u003e \u003cb\u003eEMBEDDED FLASH MEMORY\u003c\/b\u003e (\u003ci\u003eChang-Kiang (Clinton) Kuo and Ko-Min Chang\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e9.1 Introduction.\u003c\/p\u003e \u003cp\u003e9.2 Embedded Flash Versus Stand-Alone Flash Memory.\u003c\/p\u003e \u003cp\u003e9.3 Embedded Flash Memory Applications.\u003c\/p\u003e \u003cp\u003e9.4 Embedded Flash Memory Cells.\u003c\/p\u003e \u003cp\u003e9.5 Embedded Flash Memory Design.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10\u003c\/b\u003e \u003cb\u003eTUNNEL DIELECTRICS FOR SCALED FLASH MEMORY CELLS\u003c\/b\u003e (\u003ci\u003eT. P. Ma\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e10.1 Introduction.\u003c\/p\u003e \u003cp\u003e10.2 SiO2 as Tunnel Dielectric—Historical Perspective.\u003c\/p\u003e \u003cp\u003e10.3 Early Work on Silicon Nitride as a Tunnel Dielectric.\u003c\/p\u003e \u003cp\u003e10.4 Jet-Vapor Deposition Silicon Nitride Deposition.\u003c\/p\u003e \u003cp\u003e10.5 Properties of Gate-Quality JVD Silicon Nitride Films.\u003c\/p\u003e \u003cp\u003e10.6 Deposited Silicon Nitride as Tunnel Dielectric.\u003c\/p\u003e \u003cp\u003e10.7 N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.\u003c\/p\u003e \u003cp\u003e10.8 P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.\u003c\/p\u003e \u003cp\u003e10.9 Reliability Concerns Associated with Hot-Hole Injection.\u003c\/p\u003e \u003cp\u003e10.10 Tunnel Dielectric for SONOS Cell.\u003c\/p\u003e \u003cp\u003e10.11 Prospects for High-K Dielectrics.\u003c\/p\u003e \u003cp\u003e10.12 Tunnel Barrier Engineering with Multiple Barriers.\u003c\/p\u003e \u003cp\u003e10.13 Summary.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11\u003c\/b\u003e \u003cb\u003eFLASH MEMORY RELIABILITY\u003c\/b\u003e (\u003ci\u003eJian Justin Chen, Neal R. Mielke, and Chenming Calvin Hu\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e11.1 Introduction.\u003c\/p\u003e \u003cp\u003e11.2 Cycling-Induced Degradations in Flash Memories.\u003c\/p\u003e \u003cp\u003e11.3 Flash Memory Data Retention.\u003c\/p\u003e \u003cp\u003e11.4 Flash Memory Disturbs.\u003c\/p\u003e \u003cp\u003e11.5 Stress-Induced Tunnel Oxide Leakage Current.\u003c\/p\u003e \u003cp\u003e11.6 Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program.\u003c\/p\u003e \u003cp\u003e11.7 Process Impacts on Flash Memory Reliability.\u003c\/p\u003e \u003cp\u003e11.8 High-Voltage Periphery Transistor Reliability.\u003c\/p\u003e \u003cp\u003e11.9 Design and System Impacts on Flash Memory Reliability.\u003c\/p\u003e \u003cp\u003e11.10 Flash Memory Reliability Screening and Qualifi cation.\u003c\/p\u003e \u003cp\u003e11.11 For Further Study.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12\u003c\/b\u003e \u003cb\u003eMULTILEVEL CELL DIGITAL MEMORIES\u003c\/b\u003e (\u003ci\u003eAlbert Fazio and Mark Bauer\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e12.1 Introduction.\u003c\/p\u003e \u003cp\u003e12.2 Pursuit of Low-Cost Memory.\u003c\/p\u003e \u003cp\u003e12.3 Multibit Storage Breakthrough.\u003c\/p\u003e \u003cp\u003e12.4 View of MLC Today.\u003c\/p\u003e \u003cp\u003e12.5 Low-Cost Design Implementation.\u003c\/p\u003e \u003cp\u003e12.6 Low-Cost Process Manufacturing.\u003c\/p\u003e \u003cp\u003e12.7 Standard Product Feature Set.\u003c\/p\u003e \u003cp\u003e12.8 Further Reading: Multilevel Flash Memory and Technology Scaling.\u003c\/p\u003e \u003cp\u003e12.9 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13\u003c\/b\u003e \u003cb\u003eALTERNATIVE MEMORY TECHNOLOGIES\u003c\/b\u003e (\u003ci\u003eGary F. Derbenwick and Joe E. Brewer\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e13.1 Introduction.\u003c\/p\u003e \u003cp\u003e13.2 Limitations of Flash Memory.\u003c\/p\u003e \u003cp\u003e13.3 NROM Memories.\u003c\/p\u003e \u003cp\u003e13.4 Ferroelectric Memories.\u003c\/p\u003e \u003cp\u003e13.5 Magnetic Memories.\u003c\/p\u003e \u003cp\u003e13.6 Single-Electron and Few-Electron Memories.\u003c\/p\u003e \u003cp\u003e13.7 Resistive and Hybrid CMOS\/Nanodevice Memories.\u003c\/p\u003e \u003cp\u003e13.8 NOVORAM\/FRAM Cell and Architecture.\u003c\/p\u003e \u003cp\u003e13.9 Phase Change Memories.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eIndex.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAbout the Editors.\u003c\/b\u003e\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52298052993304,"sku":"9780471770022","price":121.35,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471770022.jpg?v=1781733131","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/nonvolatile-memory-technologies-with-emphasis-on-flash-a-comprehensive-guide-to-understanding-and-using-flash-memory-devices-hardback-9780471770022","provider":"Freshly Printed Books","version":"1.0","type":"link"}