{"product_id":"nand-flash-memory-technologies-hardback-9781119132608","title":"NAND Flash Memory Technologies (Hardback) 9781119132608","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eNAND Flash Memory Technologies\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eSeiichi Aritome (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781119132608, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 9 February 2016\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e432 pages\u003cbr\u003e24.4 x 16.5 x 2.8 cm, 0.721 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cul\u003e \u003cli\u003eOffers a comprehensive overview of NAND flash memories, with insights into NAND history, technology, challenges, evolutions, and perspectives\u003c\/li\u003e \u003cli\u003eDescribes new program disturb issues, data retention, power consumption, and possible solutions for the challenges of 3D NAND flash memory\u003c\/li\u003e \u003cli\u003eWritten by an authority in NAND flash memory technology, with over 25 years’ experience\u003c\/li\u003e \u003c\/ul\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eForeword xi \u003cp\u003ePreface xv\u003c\/p\u003e \u003cp\u003eAcknowledgments xvii\u003c\/p\u003e \u003cp\u003eAbout the Author xix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Background, 1\u003c\/p\u003e \u003cp\u003e1.2 Overview, 8\u003c\/p\u003e \u003cp\u003eReferences, 10\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Principle of NAND Flash Memory 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 NAND Flash Device and Architecture, 17\u003c\/p\u003e \u003cp\u003e2.1.1 NAND Flash Memory Cell Architecture, 17\u003c\/p\u003e \u003cp\u003e2.1.2 Peripheral Device, 19\u003c\/p\u003e \u003cp\u003e2.2 Cell Operation, 21\u003c\/p\u003e \u003cp\u003e2.2.1 Read Operation, 21\u003c\/p\u003e \u003cp\u003e2.2.2 Program and Erase Operation, 21\u003c\/p\u003e \u003cp\u003e2.2.3 Program and Erase Dynamics, 28\u003c\/p\u003e \u003cp\u003e2.2.4 Program Boosting Operation, 31\u003c\/p\u003e \u003cp\u003e2.3 Multilevel Cell (MLC), 34\u003c\/p\u003e \u003cp\u003e2.3.1 Cell Vt Setting, 34\u003c\/p\u003e \u003cp\u003eReferences, 35\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 NAND Flash Memory Devices 37\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction, 37\u003c\/p\u003e \u003cp\u003e3.2 LOCOS Cell, 40\u003c\/p\u003e \u003cp\u003e3.2.1 Conventional LOCOS Cell, 40\u003c\/p\u003e \u003cp\u003e3.2.2 Advanced LOCOS Cell, 40\u003c\/p\u003e \u003cp\u003e3.2.3 Isolation Technology, 43\u003c\/p\u003e \u003cp\u003e3.2.4 Reliability, 46\u003c\/p\u003e \u003cp\u003e3.3 Self-Aligned STI Cell (SA-STI Cell) with FG Wing, 48\u003c\/p\u003e \u003cp\u003e3.3.1 Structure of SA-STI Cell, 48\u003c\/p\u003e \u003cp\u003e3.3.2 Fabrication Process Flow, 50\u003c\/p\u003e \u003cp\u003e3.3.3 Characteristics of SA-STI with FG Wing Cell, 53\u003c\/p\u003e \u003cp\u003e3.3.4 Characteristics of Peripheral Devices, 57\u003c\/p\u003e \u003cp\u003e3.4 Self-Aligned STI Cell (SA-STI Cell) without FG Wing, 59\u003c\/p\u003e \u003cp\u003e3.4.1 SA-STI Cell Structure, 59\u003c\/p\u003e \u003cp\u003e3.4.2 Fabrication Process, 60\u003c\/p\u003e \u003cp\u003e3.4.3 Shallow Trench Isolation (STI), 61\u003c\/p\u003e \u003cp\u003e3.4.4 SA-STI Cell Characteristics, 64\u003c\/p\u003e \u003cp\u003e3.5 Planar FG Cell, 66\u003c\/p\u003e \u003cp\u003e3.5.1 Structure Advantages, 66\u003c\/p\u003e \u003cp\u003e3.5.2 Electrical Characteristics, 68\u003c\/p\u003e \u003cp\u003e3.6 Sidewall Transfer Transistor Cell (SWATT Cell), 69\u003c\/p\u003e \u003cp\u003e3.6.1 Concept of the SWATT Cell, 70\u003c\/p\u003e \u003cp\u003e3.6.2 Fabrication Process, 71\u003c\/p\u003e \u003cp\u003e3.6.3 Electrical Characteristics, 74\u003c\/p\u003e \u003cp\u003e3.7 Advanced NAND Flash Device Technologies, 77\u003c\/p\u003e \u003cp\u003e3.7.1 Dummy Word Line, 77\u003c\/p\u003e \u003cp\u003e3.7.2 The P-Type Floating Gate, 82\u003c\/p\u003e \u003cp\u003eReferences, 89\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Advanced Operation for Multilevel Cell 93\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction, 93\u003c\/p\u003e \u003cp\u003e4.2 Program Operation for Tight Vt Distribution Width, 94\u003c\/p\u003e \u003cp\u003e4.2.1 Cell Vt Setting, 94\u003c\/p\u003e \u003cp\u003e4.2.2 Incremental Step Pulse Program (ISPP), 95\u003c\/p\u003e \u003cp\u003e4.2.3 Bit-by-Bit Verify Operations, 98\u003c\/p\u003e \u003cp\u003e4.2.4 Two-Step Verify Scheme, 99\u003c\/p\u003e \u003cp\u003e4.2.5 Pseudo-Pass Scheme in Page Program, 102\u003c\/p\u003e \u003cp\u003e4.3 Page Program Sequence, 104\u003c\/p\u003e \u003cp\u003e4.3.1 Original Page Program Scheme, 104\u003c\/p\u003e \u003cp\u003e4.3.2 New Page Program Scheme (1), 107\u003c\/p\u003e \u003cp\u003e4.3.3 New Page Program Scheme (2), 108\u003c\/p\u003e \u003cp\u003e4.3.4 All-Bit-Line (ABL) Architecture, 111\u003c\/p\u003e \u003cp\u003e4.4 TLC (3 Bits\/Cell), 113\u003c\/p\u003e \u003cp\u003e4.5 QLC (4 Bits\/Cell), 115\u003c\/p\u003e \u003cp\u003e4.6 Three-Level (1.5 Bits\/Cell) NAND flash, 119\u003c\/p\u003e \u003cp\u003e4.7 Moving Read Algorithm, 122\u003c\/p\u003e \u003cp\u003eReferences, 123\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Scaling Challenge of NAND Flash Memory Cells 129\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction, 129\u003c\/p\u003e \u003cp\u003e5.2 Read Window Margin (RWM), 130\u003c\/p\u003e \u003cp\u003e5.2.1 Assumption for Read Window Margin (RWM), 131\u003c\/p\u003e \u003cp\u003e5.2.2 Programmed Vt Distribution Width, 135\u003c\/p\u003e \u003cp\u003e5.2.3 Vt Window, 137\u003c\/p\u003e \u003cp\u003e5.2.4 Read Window Margin (RWM), 139\u003c\/p\u003e \u003cp\u003e5.2.5 RWM Vt Setting Dependence, 140\u003c\/p\u003e \u003cp\u003e5.3 Floating-Gate Capacitive Coupling Interference, 142\u003c\/p\u003e \u003cp\u003e5.3.1 Model of Floating-Gate Capacitive Coupling Interference, 142\u003c\/p\u003e \u003cp\u003e5.3.2 Direct Coupling with Channel, 145\u003c\/p\u003e \u003cp\u003e5.3.3 Coupling with Source\/Drain, 148\u003c\/p\u003e \u003cp\u003e5.3.4 Air Gap and Low-k Material, 149\u003c\/p\u003e \u003cp\u003e5.4 Program Electron Injection Spread, 153\u003c\/p\u003e \u003cp\u003e5.4.1 Theory of Program Electron Injection Spread, 153\u003c\/p\u003e \u003cp\u003e5.4.2 Effect of Lower Doping in FG, 158\u003c\/p\u003e \u003cp\u003e5.5 Random Telegraph Signal Noise (RTN), 161\u003c\/p\u003e \u003cp\u003e5.5.1 RTN in Flash Memory Cells, 161\u003c\/p\u003e \u003cp\u003e5.5.2 Scaling Trend of RTN, 166\u003c\/p\u003e \u003cp\u003e5.6 Cell Structure Challenge, 170\u003c\/p\u003e \u003cp\u003e5.7 High-Field Limitation, 171\u003c\/p\u003e \u003cp\u003e5.8 A Few Electron Phenomena, 175\u003c\/p\u003e \u003cp\u003e5.9 Patterning Limitation, 178\u003c\/p\u003e \u003cp\u003e5.10 Variation, 179\u003c\/p\u003e \u003cp\u003e5.11 Scaling impact on Data Retention, 183\u003c\/p\u003e \u003cp\u003e5.12 Summary, 185\u003c\/p\u003e \u003cp\u003eReferences, 186\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Reliability of NAND Flash Memory 195\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction, 195\u003c\/p\u003e \u003cp\u003e6.2 Program\/Erase Cycling Endurance and Data Retention, 198\u003c\/p\u003e \u003cp\u003e6.2.1 Program and Erase Scheme, 198\u003c\/p\u003e \u003cp\u003e6.2.2 Program and Erase Cycling Endurance, 200\u003c\/p\u003e \u003cp\u003e6.2.3 Data Retention Characteristics, 203\u003c\/p\u003e \u003cp\u003e6.3 Analysis of Program\/Erase Cycling Endurance and Data Retention, 210\u003c\/p\u003e \u003cp\u003e6.3.1 Program\/Erase Cycling Degradation, 210\u003c\/p\u003e \u003cp\u003e6.3.2 SILC (Stress-Induced Leakage Current), 216\u003c\/p\u003e \u003cp\u003e6.3.3 Data Retention in NAND Flash Product, 219\u003c\/p\u003e \u003cp\u003e6.3.4 Distributed Cycling Test, 222\u003c\/p\u003e \u003cp\u003e6.4 Read Disturb, 224\u003c\/p\u003e \u003cp\u003e6.4.1 Program\/Erase Scheme Dependence, 224\u003c\/p\u003e \u003cp\u003e6.4.2 Detrapping and SILC, 229\u003c\/p\u003e \u003cp\u003e6.4.3 Read Disturb in NAND Flash Product, 234\u003c\/p\u003e \u003cp\u003e6.4.4 Hot Carrier Injection Mechanism in Read Disturb, 235\u003c\/p\u003e \u003cp\u003e6.5 Program Disturb, 238\u003c\/p\u003e \u003cp\u003e6.5.1 Model of Self-Boosting, 238\u003c\/p\u003e \u003cp\u003e6.5.2 Hot Carrier Injection Mechanism, 244\u003c\/p\u003e \u003cp\u003e6.5.3 Channel Coupling, 248\u003c\/p\u003e \u003cp\u003e6.6 Erratic Over-Program, 250\u003c\/p\u003e \u003cp\u003e6.7 Negative Vt shift phenomena, 253\u003c\/p\u003e \u003cp\u003e6.7.1 Background and Experiment, 253\u003c\/p\u003e \u003cp\u003e6.7.2 Negative Vt Shift, 254\u003c\/p\u003e \u003cp\u003e6.7.3 Program Speed and Victim Cell Vt Dependence, 256\u003c\/p\u003e \u003cp\u003e6.7.4 Carrier Separation in Programming Conditions, 260\u003c\/p\u003e \u003cp\u003e6.7.5 Model, 262\u003c\/p\u003e \u003cp\u003e6.8 Summary, 263\u003c\/p\u003e \u003cp\u003eReferences, 266\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Three-Dimensional NAND Flash Cell 273\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Background of Three-Dimensional NAND Cells, 273\u003c\/p\u003e \u003cp\u003e7.2 BiCS (Bit Cost Scalable Technology) \/ P-BiCS (Pipe-Shape BiCS), 276\u003c\/p\u003e \u003cp\u003e7.2.1 Concept of BiCS, 276\u003c\/p\u003e \u003cp\u003e7.2.2 Fabrication Process of BiCS, 278\u003c\/p\u003e \u003cp\u003e7.2.3 Electrical Characteristics, 279\u003c\/p\u003e \u003cp\u003e7.2.4 Pipe-Shaped BiCS, 285\u003c\/p\u003e \u003cp\u003e7.3 TCAT (Terabit Cell Array Transistor)\/V-NAND (Vertical-NAND), 289\u003c\/p\u003e \u003cp\u003e7.3.1 Structure and Fabrication Process of TCAT, 289\u003c\/p\u003e \u003cp\u003e7.3.2 Electrical Characteristics, 292\u003c\/p\u003e \u003cp\u003e7.3.3 128-Gb MLC V-NAND Flash Memory, 294\u003c\/p\u003e \u003cp\u003e7.3.4 128-Gb TLC V-NAND Flash Memory, 296\u003c\/p\u003e \u003cp\u003e7.4 SMArT (Stacked Memory Array Transistor), 298\u003c\/p\u003e \u003cp\u003e7.4.1 Structural Advantage of SMArT, 298\u003c\/p\u003e \u003cp\u003e7.4.2 Electrical Characteristics, 301\u003c\/p\u003e \u003cp\u003e7.5 VG-NAND (Vertical Gate NAND Cell), 302\u003c\/p\u003e \u003cp\u003e7.5.1 Structure and Fabrication Process of VG-NAND, 302\u003c\/p\u003e \u003cp\u003e7.5.2 Electrical Characteristics, 305\u003c\/p\u003e \u003cp\u003e7.6 Dual Control Gate—Surrounding Floating Gate Cell (DC-SF Cell), 308\u003c\/p\u003e \u003cp\u003e7.6.1 Concern for Charge Trap 3D Cell, 308\u003c\/p\u003e \u003cp\u003e7.6.2 DC-SF NAND Flash Cells, 309\u003c\/p\u003e \u003cp\u003e7.6.3 Results and Discussions, 313\u003c\/p\u003e \u003cp\u003e7.6.4 Scaling Capability, 317\u003c\/p\u003e \u003cp\u003e7.7 Advanced DC-SF Cell, 317\u003c\/p\u003e \u003cp\u003e7.7.1 Improvement on DC-SF Cell, 317\u003c\/p\u003e \u003cp\u003e7.7.2 MCGL Process, 319\u003c\/p\u003e \u003cp\u003e7.7.3 New Read Scheme, 319\u003c\/p\u003e \u003cp\u003e7.7.4 New Programming Scheme, 325\u003c\/p\u003e \u003cp\u003e7.7.5 Reliability, 329\u003c\/p\u003e \u003cp\u003eReferences, 329\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Challenges of Three-Dimensional NAND Flash Memory 335\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction, 335\u003c\/p\u003e \u003cp\u003e8.2 Comparison of 3D NAND Cells, 336\u003c\/p\u003e \u003cp\u003e8.3 Data Retention, 339\u003c\/p\u003e \u003cp\u003e8.3.1 Quick Initial Charge Loss, 339\u003c\/p\u003e \u003cp\u003e8.3.2 Temperature Dependence, 342\u003c\/p\u003e \u003cp\u003e8.4 Program Disturb, 343\u003c\/p\u003e \u003cp\u003e8.4.1 New Program Disturb Modes, 343\u003c\/p\u003e \u003cp\u003e8.4.2 Analysis of Program Disturb, 345\u003c\/p\u003e \u003cp\u003e8.5 Word-Line RC Delay, 350\u003c\/p\u003e \u003cp\u003e8.6 Cell Current Fluctuation, 353\u003c\/p\u003e \u003cp\u003e8.6.1 Conduction Mechanism, 353\u003c\/p\u003e \u003cp\u003e8.6.2 VG Dependence, 358\u003c\/p\u003e \u003cp\u003e8.6.3 Random Telegraph Noise (RTN), 360\u003c\/p\u003e \u003cp\u003e8.6.4 Back-Side Trap in Macaroni Channel, 363\u003c\/p\u003e \u003cp\u003e8.6.5 Laser Thermal Anneal, 366\u003c\/p\u003e \u003cp\u003e8.7 Number of Stacked Cells, 368\u003c\/p\u003e \u003cp\u003e8.8 Peripheral Circuit Under Cell Array, 370\u003c\/p\u003e \u003cp\u003e8.9 Power Consumption, 371\u003c\/p\u003e \u003cp\u003e8.10 Future Trend of 3D NAND Flash Memory, 374\u003c\/p\u003e \u003cp\u003eReferences, 376\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Conclusions 381\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Discussions and Conclusions, 381\u003c\/p\u003e \u003cp\u003e9.2 Perspective, 384\u003c\/p\u003e \u003cp\u003eReferences, 385\u003c\/p\u003e \u003cp\u003eIndex 389\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52421420056856,"sku":"9781119132608","price":96.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781119132608.jpg?v=1784595677","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/nand-flash-memory-technologies-hardback-9781119132608","provider":"Freshly Printed Books","version":"1.0","type":"link"}