{"product_id":"multi-processor-system-on-chip-2-applications-hardback-9781789450224","title":"Multi-Processor System-on-Chip 2; Applications (Hardback) 9781789450224","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eMulti-Processor System-on-Chip 2\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eApplications\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eLiliana Andrade (Edited by), L Andrade (Author), Frederic Rousseau (Edited by)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781789450224, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 11 May 2021\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e272 pages\u003cbr\u003e1 x 1 x 1 cm, 0.454 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eA Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes – Architectures and Applications – therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. \u003cp\u003e\u003ci\u003eMulti-Processor System-on-Chip 2\u003c\/i\u003e covers application-specific MPSoC design, including compilers and architecture exploration. This second volume describes optimization methods, tools to optimize and port specific applications on MPSoC architectures. Details on compilation, power consumption and wireless communication are also presented, as well as examples of modeling frameworks and CAD tools. Explanations of specific platforms for automotive and real-time computing are also included.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eForeword xi\u003cbr\u003e\u003ci\u003eAhmed JERRAYA\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eAcknowledgments xiii\u003cbr\u003e\u003ci\u003eLiliana ANDRADE and Frédéric ROUSSEAU\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 1. MPSoC for Telecom 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1. From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 3\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eStefan A. DAMJANCEVIC, Emil MATUS, Dmitry UTYANSKY, Pieter VAN DER WOLF and Gerhard P. FETTWEIS\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1. Introduction 4\u003c\/p\u003e \u003cp\u003e1.2. Breadth of workloads 6\u003c\/p\u003e \u003cp\u003e1.2.1. Vision, trends and applications 6\u003c\/p\u003e \u003cp\u003e1.2.2. Standard specifications 8\u003c\/p\u003e \u003cp\u003e1.2.3. Outcome of workloads 13\u003c\/p\u003e \u003cp\u003e1.3. GFDM algorithm breakdown 14\u003c\/p\u003e \u003cp\u003e1.3.1. Equation 15\u003c\/p\u003e \u003cp\u003e1.3.2. Dataflow processing graph and matrix representation 15\u003c\/p\u003e \u003cp\u003e1.3.3. Pseudo-code 16\u003c\/p\u003e \u003cp\u003e1.4. Algorithm precision requirements and considerations 18\u003c\/p\u003e \u003cp\u003e1.5. Implementation 21\u003c\/p\u003e \u003cp\u003e1.5.1. Implementation considerations 23\u003c\/p\u003e \u003cp\u003e1.5.2. Design space exploration 23\u003c\/p\u003e \u003cp\u003e1.5.3. Measurements for low-end and high-end use cases 26\u003c\/p\u003e \u003cp\u003e1.6. Conclusion 28\u003c\/p\u003e \u003cp\u003e1.7. Acknowledgments 29\u003c\/p\u003e \u003cp\u003e1.8. References 29\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2. Towards Tbit\/s Wireless Communication Baseband Processing: When Shannon meets Moore 33\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eMatthias HERRMANN and Norbert WEHN\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1. Introduction 34\u003c\/p\u003e \u003cp\u003e2.2. Role of microelectronics 36\u003c\/p\u003e \u003cp\u003e2.3. Towards 1 Tbit\/s throughput decoders 37\u003c\/p\u003e \u003cp\u003e2.3.1. Turbodecoder 39\u003c\/p\u003e \u003cp\u003e2.3.2. LDPC  decoder 41\u003c\/p\u003e \u003cp\u003e2.3.3. Polar decoder 41\u003c\/p\u003e \u003cp\u003e2.4. Conclusion 43\u003c\/p\u003e \u003cp\u003e2.5. Acknowledgments 43\u003c\/p\u003e \u003cp\u003e2.6. References 43\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 2. Application-specific MPSoC Architectures 47\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3. Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 49\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eMarcello COPPOLA and George KORNAROS\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1. Introduction 50\u003c\/p\u003e \u003cp\u003e3.2. Security in IIoT 52\u003c\/p\u003e \u003cp\u003e3.3. LoRaWAN security in IIoT 53\u003c\/p\u003e \u003cp\u003e3.4. Threatmodel 55\u003c\/p\u003e \u003cp\u003e3.4.1. LoRaWAN attack model 55\u003c\/p\u003e \u003cp\u003e3.4.2. IIoT node attack model 56\u003c\/p\u003e \u003cp\u003e3.5. Trusted boot chain with STM32MP1 57\u003c\/p\u003e \u003cp\u003e3.5.1. Trust base of node 57\u003c\/p\u003e \u003cp\u003e3.5.2. Trusted firmware inSTM32MP1 57\u003c\/p\u003e \u003cp\u003e3.5.3. Trusted execution environments and OP-TEE 58\u003c\/p\u003e \u003cp\u003e3.5.4. OP-TEE scheduling considerations 60\u003c\/p\u003e \u003cp\u003e3.5.5. OP-TEEmemorymanagement 60\u003c\/p\u003e \u003cp\u003e3.5.6. OP-TEE clientAPI 61\u003c\/p\u003e \u003cp\u003e3.5.7.TEE internal coreAPI 62\u003c\/p\u003e \u003cp\u003e3.5.8. Root and chain of trust 62\u003c\/p\u003e \u003cp\u003e3.5.9. Hardware unique key 62\u003c\/p\u003e \u003cp\u003e3.5.10.  Secure clock 63\u003c\/p\u003e \u003cp\u003e3.5.11. Cryptographic operations 63\u003c\/p\u003e \u003cp\u003e3.6. LoRaWAN gateway  withSTM32MP1 64\u003c\/p\u003e \u003cp\u003e3.7. Discussion and future scope 65\u003c\/p\u003e \u003cp\u003e3.8. Acknowledgments 66\u003c\/p\u003e \u003cp\u003e3.9. References 66\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4. Accelerating Virtualized Distributed NVMe Storage in Hardware 69\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eJulian CHESTERFIELD and Michail FLOURIS\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1. Introduction 70\u003c\/p\u003e \u003cp\u003e4.1.1. Virtualization and traditional hypervisors 71\u003c\/p\u003e \u003cp\u003e4.1.2. Hyperconverged versus disaggregated cloud architectures 72\u003c\/p\u003e \u003cp\u003e4.1.3. NVMe flash storage 74\u003c\/p\u003e \u003cp\u003e4.2. Motivation:NVMe storage for the cloud 75\u003c\/p\u003e \u003cp\u003e4.2.1. Motivation for a new hypervisor 75\u003c\/p\u003e \u003cp\u003e4.2.2. Motivation for accelerating disaggregated storage 76\u003c\/p\u003e \u003cp\u003e4.3. Design 77\u003c\/p\u003e \u003cp\u003e4.3.1. Optimizing the hypervisor I\/O operations 77\u003c\/p\u003e \u003cp\u003e4.3.2. Design of accelerated disaggregated storage 80\u003c\/p\u003e \u003cp\u003e4.4. Implementation 86\u003c\/p\u003e \u003cp\u003e4.4.1. The NexVisor platform 87\u003c\/p\u003e \u003cp\u003e4.4.2. Accelerated disaggregated storage 87\u003c\/p\u003e \u003cp\u003e4.5. Results 90\u003c\/p\u003e \u003cp\u003e4.5.1. Sequential reads 90\u003c\/p\u003e \u003cp\u003e4.5.2.  Sequentialwrites 90\u003c\/p\u003e \u003cp\u003e4.5.3. Sequential reads on one NVMe drive 92\u003c\/p\u003e \u003cp\u003e4.5.4. Networkperformance 92\u003c\/p\u003e \u003cp\u003e4.6. Conclusion 93\u003c\/p\u003e \u003cp\u003e4.7. References 93\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5. Modular and Open Platform for Future Automotive Computing Environment 95\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eRaphaël DAVID, Etienne HAMELIN, Paul DUBRULLE, Shuai LI, Philippe DORE, Alexis OLIVEREAU, Maroun OJAIL, Alexandre CARBON and Laurent LE GARFF\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1. Introduction 96\u003c\/p\u003e \u003cp\u003e5.2. Outline of this approach 98\u003c\/p\u003e \u003cp\u003e5.2.1. Centralized computation, distributed data 98\u003c\/p\u003e \u003cp\u003e5.2.2. Modularity and heterogeneity 99\u003c\/p\u003e \u003cp\u003e5.2.3. Tools for specification, configuration and integration 101\u003c\/p\u003e \u003cp\u003e5.3. Results 102\u003c\/p\u003e \u003cp\u003e5.3.1. Hardware platform 103\u003c\/p\u003e \u003cp\u003e5.3.2. FACE SW architecture 108\u003c\/p\u003e \u003cp\u003e5.3.3. FACE Tool Suite 112\u003c\/p\u003e \u003cp\u003e5.4. Use case 116\u003c\/p\u003e \u003cp\u003e5.4.1. Adaptive braking system 116\u003c\/p\u003e \u003cp\u003e5.5. Conclusion 118\u003c\/p\u003e \u003cp\u003e5.6. References 119\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6. Post-Moore Datacenter Server Architecture 123\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eBabak FALSAFI\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1. Introduction 124\u003c\/p\u003e \u003cp\u003e6.2. Background: today’s blades are from the desktops of the 1980s 125\u003c\/p\u003e \u003cp\u003e6.3. Memory-centricserverdesign 127\u003c\/p\u003e \u003cp\u003e6.4. Data management accelerators 129\u003c\/p\u003e \u003cp\u003e6.5. Integrated network controllers 130\u003c\/p\u003e \u003cp\u003e6.6. References 131\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 3. Architecture Examples and Tools for MPSoC 135\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7. SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping 137\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eAmir CHARIF, AriefWICAKSANA, Salah-Eddine SAIDI, Tanguy SASSOLAS, Caaliph ANDRIAMISAINA and Nicolas VENTROUX\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1. Introduction 138\u003c\/p\u003e \u003cp\u003e7.2. An overview of the SESAM platform 138\u003c\/p\u003e \u003cp\u003e7.2.1. Multi-abstraction system prototyping 139\u003c\/p\u003e \u003cp\u003e7.2.2. Assessing extra-functional system properties 140\u003c\/p\u003e \u003cp\u003e7.3. VPSim: fast and easy virtual prototyping 140\u003c\/p\u003e \u003cp\u003e7.3.1. Writing peripherals in Python 141\u003c\/p\u003e \u003cp\u003e7.3.2. The Model Provider interface 142\u003c\/p\u003e \u003cp\u003e7.3.3. QEMU support 144\u003c\/p\u003e \u003cp\u003e7.3.4. Online simulation monitoring 146\u003c\/p\u003e \u003cp\u003e7.3.5. Acceleration methods 146\u003c\/p\u003e \u003cp\u003e7.4. Hybrid prototyping 147\u003c\/p\u003e \u003cp\u003e7.4.1. Co-simulationmode 148\u003c\/p\u003e \u003cp\u003e7.4.2. Co-emulationmode 149\u003c\/p\u003e \u003cp\u003e7.4.3. Runtime performance analysis and debugging features 149\u003c\/p\u003e \u003cp\u003e7.5.FMI for co-simulation 150\u003c\/p\u003e \u003cp\u003e7.5.1. Functional mock-up interface 151\u003c\/p\u003e \u003cp\u003e7.5.2. VPSim integration inFMI co-simulation 152\u003c\/p\u003e \u003cp\u003e7.6. Conclusion 155\u003c\/p\u003e \u003cp\u003e7.7. References 155\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8. StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing 157\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eKees VAN BERKEL\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8.1. Introduction 158\u003c\/p\u003e \u003cp\u003e8.2. Static dataflow 161\u003c\/p\u003e \u003cp\u003e8.2.1. Synchronous dataflow 162\u003c\/p\u003e \u003cp\u003e8.2.2. Cyclo-static dataflow 166\u003c\/p\u003e \u003cp\u003e8.2.3. Dataflow graph transformations 167\u003c\/p\u003e \u003cp\u003e8.3. Dynamic dataflow 168\u003c\/p\u003e \u003cp\u003e8.3.1. Data-dependentdataflow 168\u003c\/p\u003e \u003cp\u003e8.3.2. Non-determinatedataflow 172\u003c\/p\u003e \u003cp\u003e8.4. Dataflow execution models 175\u003c\/p\u003e \u003cp\u003e8.4.1. A brief review of dataflow theory 175\u003c\/p\u003e \u003cp\u003e8.4.2. The StaccatoLab execution model 177\u003c\/p\u003e \u003cp\u003e8.5. StaccatoLab 180\u003c\/p\u003e \u003cp\u003e8.5.1. Dataflow graph description and analysis 180\u003c\/p\u003e \u003cp\u003e8.5.2. Verilog synthesis 180\u003c\/p\u003e \u003cp\u003e8.6. Large-scale dataflow computing? 182\u003c\/p\u003e \u003cp\u003e8.6.1. What kind of applications? 182\u003c\/p\u003e \u003cp\u003e8.6.2. Why effective? 183\u003c\/p\u003e \u003cp\u003e8.6.3. Why efficient? 184\u003c\/p\u003e \u003cp\u003e8.7. Acknowledgments 185\u003c\/p\u003e \u003cp\u003e8.8. References 185\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9. Smart Cameras and MPSoCs 189\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eMarilyn WOLF\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9.1. Introduction 189\u003c\/p\u003e \u003cp\u003e9.2. Early VLSI video processors 190\u003c\/p\u003e \u003cp\u003e9.3. Video signal processors 191\u003c\/p\u003e \u003cp\u003e9.4. Accelerators 193\u003c\/p\u003e \u003cp\u003e9.5. From VSP to  MPSoC 195\u003c\/p\u003e \u003cp\u003e9.6. Graphics processing units 197\u003c\/p\u003e \u003cp\u003e9.7. Neural networks and tensor processing units 197\u003c\/p\u003e \u003cp\u003e9.8. Conclusion 199\u003c\/p\u003e \u003cp\u003e9.9. References 199\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10. Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms 203\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eWeihua SHENG, Jeronimo CASTRILLON and Rainer LEUPERS\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10.1. Introduction 204\u003c\/p\u003e \u003cp\u003e10.2. Dataflow modeling 207\u003c\/p\u003e \u003cp\u003e10.2.1. General concepts 207\u003c\/p\u003e \u003cp\u003e10.2.2. Process networks 208\u003c\/p\u003e \u003cp\u003e10.2.3. Cfor process networks 209\u003c\/p\u003e \u003cp\u003e10.3. Source-to-source-based compiler infrastructure 214\u003c\/p\u003e \u003cp\u003e10.3.1.Design rationale 214\u003c\/p\u003e \u003cp\u003e10.3.2. Implementation strategy 216\u003c\/p\u003e \u003cp\u003e10.4. Software distribution 218\u003c\/p\u003e \u003cp\u003e10.4.1. KPNanalysis 219\u003c\/p\u003e \u003cp\u003e10.4.2. Static KPN mapping 220\u003c\/p\u003e \u003cp\u003e10.4.3. Hybrid KPN mapping 221\u003c\/p\u003e \u003cp\u003e10.5. Results 222\u003c\/p\u003e \u003cp\u003e10.5.1.Applications and experiences 222\u003c\/p\u003e \u003cp\u003e10.5.2. Retargetability 229\u003c\/p\u003e \u003cp\u003e10.6. Conclusion 230\u003c\/p\u003e \u003cp\u003e10.7. References 231\u003c\/p\u003e \u003cp\u003eList of Authors 237\u003c\/p\u003e \u003cp\u003eAuthor Biographies 241\u003c\/p\u003e \u003cp\u003eIndex 251\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-ISTE","offers":[{"title":"Brand New","offer_id":52446802018584,"sku":"9781789450224","price":99.89,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781789450224.jpg?v=1785114174","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/multi-processor-system-on-chip-2-applications-hardback-9781789450224","provider":"Freshly Printed Books","version":"1.0","type":"link"}