{"product_id":"multi-processor-system-on-chip-1-architectures-hardback-9781789450217","title":"Multi-Processor System-on-Chip 1; Architectures (Hardback) 9781789450217","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eMulti-Processor System-on-Chip 1\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eArchitectures\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eLiliana Andrade (Edited by), L Andrade (Author), Frederic Rousseau (Edited by)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781789450217, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 7 May 2021\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e320 pages\u003cbr\u003e1 x 1 x 1 cm, 0.454 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eA Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes – Architectures and Applications – therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eMulti-Processor System-on-Chip 1\u003c\/i\u003e covers the key components of MPSoC: processors, memory, interconnect and interfaces. It describes advance features of these components and technologies to build efficient MPSoC architectures. All the main components are detailed: use of memory and their technology, communication support and consistency, and specific processor architectures for general purposes or for dedicated applications.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eForeword xiii\u003cbr\u003e\u003ci\u003eAhmed JERRAYA\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eAcknowledgments xv\u003cbr\u003e\u003ci\u003eLiliana ANDRADE and Frédéric ROUSSEAU\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 1. Processors 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1. Processors for the Internet of Things 3\u003cbr\u003e\u003c\/b\u003e\u003ci\u003ePieter VAN DER WOLF and Yankin TANURHAN\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1. Introduction 3\u003c\/p\u003e \u003cp\u003e1.2. Versatile processors for low-power IoT edge devices 4\u003c\/p\u003e \u003cp\u003e1.2.1. Control processing, DSP and machine learning 4\u003c\/p\u003e \u003cp\u003e1.2.2. Configurability and extensibility 6\u003c\/p\u003e \u003cp\u003e1.3. Machine learning inference 8\u003c\/p\u003e \u003cp\u003e1.3.1. Requirements for low\/mid-end machine learning inference 10\u003c\/p\u003e \u003cp\u003e1.3.2. Processor capabilities for low-power machine learning inference 14\u003c\/p\u003e \u003cp\u003e1.3.3. A software library for machine learning inference 17\u003c\/p\u003e \u003cp\u003e1.3.4. Example machine learning applications and benchmarks 20\u003c\/p\u003e \u003cp\u003e1.4. Conclusion 23\u003c\/p\u003e \u003cp\u003e1.5. References 24\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2. A Qualitative Approach to Many-core Architecture 27\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eBenoît DUPONT DE DINECHIN\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1. Introduction 28\u003c\/p\u003e \u003cp\u003e2.2. Motivations and context 29\u003c\/p\u003e \u003cp\u003e2.2.1. Many-core processors 29\u003c\/p\u003e \u003cp\u003e2.2.2. Machine learning inference 30\u003c\/p\u003e \u003cp\u003e2.2.3. Application requirements 32\u003c\/p\u003e \u003cp\u003e2.3. The MPPA3 many-core processor 34\u003c\/p\u003e \u003cp\u003e2.3.1. Global architecture 34\u003c\/p\u003e \u003cp\u003e2.3.2. Compute cluster 36\u003c\/p\u003e \u003cp\u003e2.3.3. VLIW core 38\u003c\/p\u003e \u003cp\u003e2.3.4. Coprocessor 39\u003c\/p\u003e \u003cp\u003e2.4. The MPPA3 software environments 42\u003c\/p\u003e \u003cp\u003e2.4.1. High-performance computing 42\u003c\/p\u003e \u003cp\u003e2.4.2. KaNN code generator 43\u003c\/p\u003e \u003cp\u003e2.4.3. High-integrity computing 46\u003c\/p\u003e \u003cp\u003e2.5. Conclusion 47\u003c\/p\u003e \u003cp\u003e2.6. References 48\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3. The Plural Many-core Architecture – High Performance at Low Power 53\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eRan GINOSAR\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1. Introduction 54\u003c\/p\u003e \u003cp\u003e3.2. Related works 55\u003c\/p\u003e \u003cp\u003e3.3. Plural many-core architecture 55\u003c\/p\u003e \u003cp\u003e3.4. Plural programming model 56\u003c\/p\u003e \u003cp\u003e3.5. Plural hardware scheduler\/synchronizer 58\u003c\/p\u003e \u003cp\u003e3.6. Plural networks-on-chip 61\u003c\/p\u003e \u003cp\u003e3.6.1. Schedule rNoC 61\u003c\/p\u003e \u003cp\u003e3.6.2. Shared memory NoC 61\u003c\/p\u003e \u003cp\u003e3.7. Hardware and software accelerators for the Plural architecture 62\u003c\/p\u003e \u003cp\u003e3.8. Plural system software 63\u003c\/p\u003e \u003cp\u003e3.9. Plural software development tools 65\u003c\/p\u003e \u003cp\u003e3.10. Matrix multiplication algorithm on the Plural architecture 65\u003c\/p\u003e \u003cp\u003e3.11. Conclusion 67\u003c\/p\u003e \u003cp\u003e3.12. References 67\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4. ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs 69\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eAndreas BYTYN, René AHLSDORF and Gerd ASCHEID\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1. Introduction 70\u003c\/p\u003e \u003cp\u003e4.2. Related works 71\u003c\/p\u003e \u003cp\u003e4.3. ASIP architecture 74\u003c\/p\u003e \u003cp\u003e4.4. Single-core scaling 75\u003c\/p\u003e \u003cp\u003e4.5. MPSoC overview 78\u003c\/p\u003e \u003cp\u003e4.6. NoC parameter exploration 79\u003c\/p\u003e \u003cp\u003e4.7. Summary and conclusion 82\u003c\/p\u003e \u003cp\u003e4.8. References 83\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 2. Memory 85\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5. Tackling the MPSoC Data Locality Challenge 87\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eSven RHEINDT, Akshay SRIVATSA, Oliver LENKE, Lars NOLTE, Thomas WILD and Andreas HERKERSDORF\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1. Motivation 88\u003c\/p\u003e \u003cp\u003e5.2. MPSoC target platform 90\u003c\/p\u003e \u003cp\u003e5.3. Related work 91\u003c\/p\u003e \u003cp\u003e5.4. Coherence-on-demand: region-based cache coherence 92\u003c\/p\u003e \u003cp\u003e5.4.1. RBCC versus global coherence 93\u003c\/p\u003e \u003cp\u003e5.4.2. OS extensions for coherence-on-demand 94\u003c\/p\u003e \u003cp\u003e5.4.3. Coherency region manager 94\u003c\/p\u003e \u003cp\u003e5.4.4. Experimental evaluations 97\u003c\/p\u003e \u003cp\u003e5.4.5. RBCC and data placement 99\u003c\/p\u003e \u003cp\u003e5.5. Near-memory acceleration 100\u003c\/p\u003e \u003cp\u003e5.5.1. Near-memory synchronization accelerator 102\u003c\/p\u003e \u003cp\u003e5.5.2. Near-memory queue management accelerator 104\u003c\/p\u003e \u003cp\u003e5.5.3. Near-memory graph copy accelerator 107\u003c\/p\u003e \u003cp\u003e5.5.4. Near-cache accelerator 110\u003c\/p\u003e \u003cp\u003e5.6. The big picture 111\u003c\/p\u003e \u003cp\u003e5.7. Conclusion 113\u003c\/p\u003e \u003cp\u003e5.8. Acknowledgments 114\u003c\/p\u003e \u003cp\u003e5.9. References 114\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6. mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture 119\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eAdi ELIAHU, Rotem BEN HUR, Ameer HAJ ALI and Shahar KVATINSKY\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1. Introduction 120\u003c\/p\u003e \u003cp\u003e6.2. MAGIC NOR gate 121\u003c\/p\u003e \u003cp\u003e6.3. In-memory algorithms for latency reduction 122\u003c\/p\u003e \u003cp\u003e6.4. Synthesis and in-memory mapping methods 123\u003c\/p\u003e \u003cp\u003e6.4.1. SIMPLE 124\u003c\/p\u003e \u003cp\u003e6.4.2. SIMPLER 126\u003c\/p\u003e \u003cp\u003e6.5. Designing the memory controller 127\u003c\/p\u003e \u003cp\u003e6.6. Conclusion 129\u003c\/p\u003e \u003cp\u003e6.7. References 130\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7. Removing Load\/Store Helpers in Dynamic Binary Translation 133\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eAntoine FARAVELON, Olivier GRUBER and Frédéric PÉTROT\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1. Introduction 134\u003c\/p\u003e \u003cp\u003e7.2. Emulating memory accesses 136\u003c\/p\u003e \u003cp\u003e7.3. Design of our solution 140\u003c\/p\u003e \u003cp\u003e7.4. Implementation 143\u003c\/p\u003e \u003cp\u003e7.4.1. Kernel module 143\u003c\/p\u003e \u003cp\u003e7.4.2. Dynamic binary translation 145\u003c\/p\u003e \u003cp\u003e7.4.3. Optimizing our slow path 147\u003c\/p\u003e \u003cp\u003e7.5. Evaluation 149\u003c\/p\u003e \u003cp\u003e7.5.1. QEMU emulation performance analysis 150\u003c\/p\u003e \u003cp\u003e7.5.2. Our performance overview 151\u003c\/p\u003e \u003cp\u003e7.5.3. Optimized slow path 153\u003c\/p\u003e \u003cp\u003e7.6. Related works 155\u003c\/p\u003e \u003cp\u003e7.7. Conclusion 157\u003c\/p\u003e \u003cp\u003e7.8. References 158\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8. Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures 161\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eArthur VIANES and Frédéric ROUSSEAU\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8.1. Introduction 162\u003c\/p\u003e \u003cp\u003e8.1.1. Context 162\u003c\/p\u003e \u003cp\u003e8.1.2. MPSoC architecture 163\u003c\/p\u003e \u003cp\u003e8.1.3. Interconnect 164\u003c\/p\u003e \u003cp\u003e8.2. Basics on banked memory 165\u003c\/p\u003e \u003cp\u003e8.2.1. Banked memory 165\u003c\/p\u003e \u003cp\u003e8.2.2. Memory bank conflict and granularity 166\u003c\/p\u003e \u003cp\u003e8.2.3. Efficient use of memory banks: interleaving 168\u003c\/p\u003e \u003cp\u003e8.3. Overview of software approaches 170\u003c\/p\u003e \u003cp\u003e8.3.1. Padding 170\u003c\/p\u003e \u003cp\u003e8.3.2. Static scheduling of memory accesses 172\u003c\/p\u003e \u003cp\u003e8.3.3. The need for hardware approaches 172\u003c\/p\u003e \u003cp\u003e8.4. Hardware approaches 172\u003c\/p\u003e \u003cp\u003e8.4.1. Prime modulus indexing 172\u003c\/p\u003e \u003cp\u003e8.4.2. Interleaving schemes using hash functions 174\u003c\/p\u003e \u003cp\u003e8.5. Modeling and experimenting 181\u003c\/p\u003e \u003cp\u003e8.5.1. Simulator implementation 182\u003c\/p\u003e \u003cp\u003e8.5.2. Implementation of the Kalray MPPA cluster interconnect 182\u003c\/p\u003e \u003cp\u003e8.5.3. Objectives and method 184\u003c\/p\u003e \u003cp\u003e8.5.4. Results and discussion 185\u003c\/p\u003e \u003cp\u003e8.6. Conclusion 191\u003c\/p\u003e \u003cp\u003e8.7. References 192\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 3. Interconnect and Interfaces 195\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9. Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs) 197\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eK. Charles JANAC\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9.1. History: transition from buses and crossbars to NoCs 198\u003c\/p\u003e \u003cp\u003e9.1.1.NoC architecture 202\u003c\/p\u003e \u003cp\u003e9.1.2. Extending the bus comparison to crossbars 207\u003c\/p\u003e \u003cp\u003e9.1.3. Bus, crossbar and NoC comparison summary and conclusion 207\u003c\/p\u003e \u003cp\u003e9.2. NoC configurability 208\u003c\/p\u003e \u003cp\u003e9.2.1. Human-guided design flow 208\u003c\/p\u003e \u003cp\u003e9.2.2. Physical placement awareness and NoC architecture design 209\u003c\/p\u003e \u003cp\u003e9.3. System-level services 211\u003c\/p\u003e \u003cp\u003e9.3.1. Quality-of-service (QoS) and arbitration 211\u003c\/p\u003e \u003cp\u003e9.3.2. Hardware debug and performance analysis 212\u003c\/p\u003e \u003cp\u003e9.3.3. Functional safety and security 212\u003c\/p\u003e \u003cp\u003e9.4. Hardware cache coherence 215\u003c\/p\u003e \u003cp\u003e9.4.1. NoC protocols, semantics and messaging 216\u003c\/p\u003e \u003cp\u003e9.5. Future NoC technology developments 217\u003c\/p\u003e \u003cp\u003e9.5.1. Topology synthesis and floorplan awareness 217\u003c\/p\u003e \u003cp\u003e9.5.2. Advanced resilience and functional safety for autonomous vehicles 218\u003c\/p\u003e \u003cp\u003e9.5.3. Alternatives to von Neumann architectures for SoCs 219\u003c\/p\u003e \u003cp\u003e9.5.4. Chiplets and multi-die NoC connectivity 221\u003c\/p\u003e \u003cp\u003e9.5.5. Runtime software automation 222\u003c\/p\u003e \u003cp\u003e9.5.6. Instrumentation, diagnostics and analytics for performance, safety and security 223\u003c\/p\u003e \u003cp\u003e9.6. Summary and conclusion 224\u003c\/p\u003e \u003cp\u003e9.7. References 224\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10. Minimum Energy Computing via Supply and Threshold Voltage Scaling 227\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eJun SHIOMI and Tohru ISHIHARA\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10.1. Introduction 228\u003c\/p\u003e \u003cp\u003e10.2. Standard-cell-based memory for minimum energy computing 230\u003c\/p\u003e \u003cp\u003e10.2.1. Overview of low-voltage on-chip memories 230\u003c\/p\u003e \u003cp\u003e10.2.2. Design strategy for area- and energy-efficient SCMs 234\u003c\/p\u003e \u003cp\u003e10.2.3. Hybrid memory design towards energy- and area-efficient memory systems 236\u003c\/p\u003e \u003cp\u003e10.2.4. Body biasing as an alternative to power gating 237\u003c\/p\u003e \u003cp\u003e10.3. Minimum energy point tracking 238\u003c\/p\u003e \u003cp\u003e10.3.1. Basic theory 238\u003c\/p\u003e \u003cp\u003e10.3.2. Algorithms and implementation 244\u003c\/p\u003e \u003cp\u003e10.3.3. OS-based approach to minimum energy point tracking 246\u003c\/p\u003e \u003cp\u003e10.4. Conclusion 249\u003c\/p\u003e \u003cp\u003e10.5. Acknowledgments 249\u003c\/p\u003e \u003cp\u003e10.6. References 250\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11. Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices 255\u003cbr\u003e\u003c\/b\u003e\u003ci\u003eArief WICAKSANA, OlivierMULLER, Frédéric ROUSSEAU and Arif SASONGKO\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e11.1. Introduction 256\u003c\/p\u003e \u003cp\u003e11.1.1. Reconfigurable architectures 256\u003c\/p\u003e \u003cp\u003e11.1.2. Contribution 257\u003c\/p\u003e \u003cp\u003e11.2. Background 257\u003c\/p\u003e \u003cp\u003e11.2.1. Definitions 258\u003c\/p\u003e \u003cp\u003e11.2.2. Problem scenario and technical challenges 259\u003c\/p\u003e \u003cp\u003e11.3. Related works 261\u003c\/p\u003e \u003cp\u003e11.3.1. Hardware context switch 261\u003c\/p\u003e \u003cp\u003e11.3.2. Communication management 262\u003c\/p\u003e \u003cp\u003e11.4. Proposed communication methodology in hardware context switching 263\u003c\/p\u003e \u003cp\u003e11.5. Implementation of the communication management on reconfigurable computing architectures 266\u003c\/p\u003e \u003cp\u003e11.5.1. Reconfigurable channels in FIFO 267\u003c\/p\u003e \u003cp\u003e11.5.2. Communication infrastructure 268\u003c\/p\u003e \u003cp\u003e11.6. Experimental results 269\u003c\/p\u003e \u003cp\u003e11.6.1. Setup 269\u003c\/p\u003e \u003cp\u003e11.6.2. Experiment scenario 270\u003c\/p\u003e \u003cp\u003e11.6.3. Resource overhead 271\u003c\/p\u003e \u003cp\u003e11.6.4. Impact on the total execution time 273\u003c\/p\u003e \u003cp\u003e11.6.5. Impact on the context extract and restore time 275\u003c\/p\u003e \u003cp\u003e11.6.6. System responsiveness to context switch requests 276\u003c\/p\u003e \u003cp\u003e11.6.7. Hardware task migration between heterogeneous FPGAs 280\u003c\/p\u003e \u003cp\u003e11.7. Conclusion 282\u003c\/p\u003e \u003cp\u003e11.8. References 283\u003c\/p\u003e \u003cp\u003eList of Authors 287\u003c\/p\u003e \u003cp\u003eAuthors Biographies 291\u003c\/p\u003e \u003cp\u003eIndex 299\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-ISTE","offers":[{"title":"Brand New","offer_id":52446801985816,"sku":"9781789450217","price":99.89,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781789450217.jpg?v=1785114173","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/multi-processor-system-on-chip-1-architectures-hardback-9781789450217","provider":"Freshly Printed Books","version":"1.0","type":"link"}