{"product_id":"modern-receiver-front-ends-systems-circuits-and-integration-hardback-9780471225911","title":"Modern Receiver Front-Ends; Systems, Circuits, and Integration (Hardback) 9780471225911","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eModern Receiver Front-Ends\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eSystems, Circuits, and Integration\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eJoy Laskar (Author), Babak Matinpour (Author), Sudipto Chakraborty (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471225911, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 5 March 2004\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e234 pages\u003cbr\u003e24.1 x 16.5 x 1.6 cm, 0.504 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cem\u003e\u003cfont size=\"3\"\u003e\"Such a book will be helpful for the understanding of receiver front-end development and architectural trade-offs.\" (\u003ci\u003eMicrowave Journal\u003c\/i\u003e, September 2004)  \u003cp\u003e\"The well-written text is illustrated with numerous references. “ (\u003ci\u003eChoice\u003c\/i\u003e, June 2004, Vol. 41 No. 10)\u003c\/p\u003e\u003c\/font\u003e\u003c\/em\u003e\u003c\/p\u003e\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eArchitectures BABAK MATINPOUR and JOY LASKAR\u003cbr\u003e * Describes the actual implementation of receiver architectures from the initial design to an IC-based product\u003cbr\u003e * Presents many tricks-of-the-trade not usually covered in textbooks\u003cbr\u003e * Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis\u003cbr\u003e * Discusses architectures that are employed in modern broadband wireless systems\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cb\u003ePreface.\u003c\/b\u003e  \u003cp\u003e\u003cb\u003eAcknowledgments.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 INTRODUCTION.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Current State of the Art.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 RECEIVER SYSTEM DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Frequency Planning.\u003c\/p\u003e \u003cp\u003e2.1.1 Blockers.\u003c\/p\u003e \u003cp\u003e2.1.2 Spurs and Desensing.\u003c\/p\u003e \u003cp\u003e2.1.3 Transmitter Leakage.\u003c\/p\u003e \u003cp\u003e2.1.4 LO Leakage and Interference.\u003c\/p\u003e \u003cp\u003e2.1.5 Image.\u003c\/p\u003e \u003cp\u003e2.1.6 Half IF.\u003c\/p\u003e \u003cp\u003e2.2 Link Budget Analysis.\u003c\/p\u003e \u003cp\u003e2.2.1 Linearity.\u003c\/p\u003e \u003cp\u003e2.2.2 Noise.\u003c\/p\u003e \u003cp\u003e2.2.3 Signal-to-Noise Ratio.\u003c\/p\u003e \u003cp\u003e2.2.4 Receiver Gain.\u003c\/p\u003e \u003cp\u003e2.3 Propagation Effects.\u003c\/p\u003e \u003cp\u003e2.3.1 Path Loss.\u003c\/p\u003e \u003cp\u003e2.3.2 Multipath and Fading.\u003c\/p\u003e \u003cp\u003e2.3.3 Equalization.\u003c\/p\u003e \u003cp\u003e2.3.4 Diversity.\u003c\/p\u003e \u003cp\u003e2.3.5 Coding.\u003c\/p\u003e \u003cp\u003e2.4 Interface Planning.\u003c\/p\u003e \u003cp\u003e2.5 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 REVIEW OF RECEIVER ARCHITECTURES.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Heterodyne Receivers.\u003c\/p\u003e \u003cp\u003e3.2 Image Reject Receivers.\u003c\/p\u003e \u003cp\u003e3.2.1 Hartley Architecture.\u003c\/p\u003e \u003cp\u003e3.2.2 Weaver Architecture.\u003c\/p\u003e \u003cp\u003e3.3 Zero IF Receivers.\u003c\/p\u003e \u003cp\u003e3.4 Low IF Receivers.\u003c\/p\u003e \u003cp\u003e3.5 I ssues in Direct Conversion Receivers.\u003c\/p\u003e \u003cp\u003e3.5.1 Noise.\u003c\/p\u003e \u003cp\u003e3.5.2 LO Leakage and Radiation.\u003c\/p\u003e \u003cp\u003e3.5.3 Phase and Amplitude Imbalance.\u003c\/p\u003e \u003cp\u003e3.5.4 DC Offset.\u003c\/p\u003e \u003cp\u003e3.5.5 Intermodulations.\u003c\/p\u003e \u003cp\u003e3.6 Architecture Comparison and Trade-off.\u003c\/p\u003e \u003cp\u003e3.7 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 SILICON-BASED RECEIVER DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Receiver Architecture and Design.\u003c\/p\u003e \u003cp\u003e4.1.1 System Description and Calculations.\u003c\/p\u003e \u003cp\u003e4.1.2 Basics of OFDM.\u003c\/p\u003e \u003cp\u003e4.1.3 System Architectures.\u003c\/p\u003e \u003cp\u003e4.1.4 System Calculations.\u003c\/p\u003e \u003cp\u003e4.2 Circuit Design.\u003c\/p\u003e \u003cp\u003e4.2.1 SiGe BiCMOS Process Technology.\u003c\/p\u003e \u003cp\u003e4.2.2 LNA.\u003c\/p\u003e \u003cp\u003e4.2.3 Mixer.\u003c\/p\u003e \u003cp\u003e4.2.4 Frequency Divider.\u003c\/p\u003e \u003cp\u003e4.3 Receiver Design Steps.\u003c\/p\u003e \u003cp\u003e4.3.1 Design and Integration of Building Blocks.\u003c\/p\u003e \u003cp\u003e4.3.2 DC Conditions.\u003c\/p\u003e \u003cp\u003e4.3.3 Scattering Parameters.\u003c\/p\u003e \u003cp\u003e4.3.4 Small-Signal Performance.\u003c\/p\u003e \u003cp\u003e4.3.5 Transient Performance.\u003c\/p\u003e \u003cp\u003e4.3.6 Noise Performance.\u003c\/p\u003e \u003cp\u003e4.3.7 Linearity Performance.\u003c\/p\u003e \u003cp\u003e4.3.8 Parasitic Effects.\u003c\/p\u003e \u003cp\u003e4.3.9 Process Variation.\u003c\/p\u003e \u003cp\u003e4.3.10 50-Ω and Non-50-Ω Receivers.\u003c\/p\u003e \u003cp\u003e4.4 Layout Considerations.\u003c\/p\u003e \u003cp\u003e4.5 Characterization of Receiver Front-Ends.\u003c\/p\u003e \u003cp\u003e4.5.1 DC Test.\u003c\/p\u003e \u003cp\u003e4.5.2 Functionality Test.\u003c\/p\u003e \u003cp\u003e4.5.3 S-Parameter Test.\u003c\/p\u003e \u003cp\u003e4.5.4 Conversion Gain Test.\u003c\/p\u003e \u003cp\u003e4.5.5 Linearity Test.\u003c\/p\u003e \u003cp\u003e4.5.6 Noise Figure Test.\u003c\/p\u003e \u003cp\u003e4.5.7 I\/Q Imbalance.\u003c\/p\u003e \u003cp\u003e4.5.8 DC Offset.\u003c\/p\u003e \u003cp\u003e4.6 Measurement Results and Discussions.\u003c\/p\u003e \u003cp\u003e4.6.1 Close Examination of Noise Figure and I\/Q Imbalance.\u003c\/p\u003e \u003cp\u003e4.6.2 Comments on I\/Q Imbalance.\u003c\/p\u003e \u003cp\u003e4.7 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 SUBHARMONIC RECEIVER DESIGNS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Illustration of Subharmonic Techniques.\u003c\/p\u003e \u003cp\u003e5.2 Mixing Using Antisymmetric I–V Characteristics.\u003c\/p\u003e \u003cp\u003e5.3 Impact of Mismatch Effects.\u003c\/p\u003e \u003cp\u003e5.4 DC Offset Cancellation Mechanisms.\u003c\/p\u003e \u003cp\u003e5.4.1 Intrinsic DC Offset Cancellation.\u003c\/p\u003e \u003cp\u003e5.4.2 Extrinsic DC Offset Cancellation.\u003c\/p\u003e \u003cp\u003e5.5 Experimental Verification of DC Offset.\u003c\/p\u003e \u003cp\u003e5.6 Waveform Shaping Before Mixing.\u003c\/p\u003e \u003cp\u003e5.6.1 Theory and Analysis.\u003c\/p\u003e \u003cp\u003e5.6.2 Experimental Verification on GaAs MESFET APDP.\u003c\/p\u003e \u003cp\u003e5.6.3 Implementation in Silicon.\u003c\/p\u003e \u003cp\u003e5.7 Design Steps for APDP-Based Receivers.\u003c\/p\u003e \u003cp\u003e5.8 Architectural Illustration.\u003c\/p\u003e \u003cp\u003e5.9 Fully Monolithic Receiver Design Using Passive APDP Cores.\u003c\/p\u003e \u003cp\u003e5.9.1 Integrated Direct Conversion Receiver MMIC’s.\u003c\/p\u003e \u003cp\u003e5.9.2 Receiver Blocks.\u003c\/p\u003e \u003cp\u003e5.9.3 Additional Receiver Blocks.\u003c\/p\u003e \u003cp\u003e5.10 Reconfigurable Multiband Subharmonic Front-Ends.\u003c\/p\u003e \u003cp\u003e5.11 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 ACTIVE SUBHARMONIC RECEIVER DESIGNS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Stacking of Switching Cores.\u003c\/p\u003e \u003cp\u003e6.1.1 Description and Principles.\u003c\/p\u003e \u003cp\u003e6.1.2 Subharmonic Receiver Architecture.\u003c\/p\u003e \u003cp\u003e6.2 Parallel Transistor Stacks.\u003c\/p\u003e \u003cp\u003e6.2.1 Active Mixer.\u003c\/p\u003e \u003cp\u003e6.2.2 Receiver Architecture.\u003c\/p\u003e \u003cp\u003e6.2.3 Extension to Passive Mixers.\u003c\/p\u003e \u003cp\u003e6.3 Extension to Higher-Order LO Subharmonics.\u003c\/p\u003e \u003cp\u003e6.4 Multiple Phase Signal Generation from Oscillators.\u003c\/p\u003e \u003cp\u003e6.5 Future Direction and Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 DESIGN AND INTEGRATION OF PASSIVE COMPONENTS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 System on Package (SoP).\u003c\/p\u003e \u003cp\u003e7.1.1 Multilayer Bandpass Filter.\u003c\/p\u003e \u003cp\u003e7.1.2 Multilayer Balun Structure.\u003c\/p\u003e \u003cp\u003e7.1.3 Module-Integrable Antennaw.\u003c\/p\u003e \u003cp\u003e7.1.4 Fully Integrated SoP Module.\u003c\/p\u003e \u003cp\u003e7.2 On-Chip Inductors.\u003c\/p\u003e \u003cp\u003e7.2.1 Inductor Modeling.\u003c\/p\u003e \u003cp\u003e7.2.2 Inductor Parameters.\u003c\/p\u003e \u003cp\u003e7.2.3 Application in Circuits.\u003c\/p\u003e \u003cp\u003e7.3 Capacitors.\u003c\/p\u003e \u003cp\u003e7.4 Differentially Driven Inductors.\u003c\/p\u003e \u003cp\u003e7.5 Transformers.\u003c\/p\u003e \u003cp\u003e7.5.1 Electrical Parameters.\u003c\/p\u003e \u003cp\u003e7.5.2 Physical Construction.\u003c\/p\u003e \u003cp\u003e7.5.3 Electrical Models.\u003c\/p\u003e \u003cp\u003e7.5.4 Frequency Response of Transformers.\u003c\/p\u003e \u003cp\u003e7.5.5 Step-Up\/Step-Down Transformers and Circuit Applications.\u003c\/p\u003e \u003cp\u003e7.6 On-Chip Filters.\u003c\/p\u003e \u003cp\u003e7.6.1 Filters Using Bond Wires.\u003c\/p\u003e \u003cp\u003e7.6.2 Active Filters.\u003c\/p\u003e \u003cp\u003e7.7 On-Wafer Antennas.\u003c\/p\u003e \u003cp\u003e7.8 Wafer-Level Packaging.\u003c\/p\u003e \u003cp\u003e7.9 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 DESIGN FOR INTEGRATION.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 System Design Considerations.\u003c\/p\u003e \u003cp\u003e8.1.1 I\/O Counts.\u003c\/p\u003e \u003cp\u003e8.1.2 Cross-Talk.\u003c\/p\u003e \u003cp\u003e8.1.3 Digital Circuitry Noise.\u003c\/p\u003e \u003cp\u003e8.2 IC Floor Plan.\u003c\/p\u003e \u003cp\u003e8.2.1 Signal Flow and Substrate Coupling.\u003c\/p\u003e \u003cp\u003e8.2.2 Grounding.\u003c\/p\u003e \u003cp\u003e8.2.3 Isolation.\u003c\/p\u003e \u003cp\u003e8.3 Packaging Considerations.\u003c\/p\u003e \u003cp\u003e8.3.1 Package Modeling.\u003c\/p\u003e \u003cp\u003e8.3.2 Bonding Limitation.\u003c\/p\u003e \u003cp\u003e8.4 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 FUTURE TRENDS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 CMOS Cellphones.\u003c\/p\u003e \u003cp\u003e9.2 Multiband, Multimode Wireless Solutions.\u003c\/p\u003e \u003cp\u003e9.3 60 GHz Subsystems in Silicon!\u003c\/p\u003e \u003cp\u003e9.4 Interchip Communications.\u003c\/p\u003e \u003cp\u003e9.5 Ultrawideband Communication Technology.\u003c\/p\u003e \u003cp\u003e9.6 Diversity Techniques.\u003c\/p\u003e \u003cp\u003e9.7 Conclusion.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eIndex.\u003c\/b\u003e\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-Interscience","offers":[{"title":"Brand New","offer_id":52286320935192,"sku":"9780471225911","price":104.39,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471225911.jpg?v=1781549876","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/modern-receiver-front-ends-systems-circuits-and-integration-hardback-9780471225911","provider":"Freshly Printed Books","version":"1.0","type":"link"}