{"product_id":"low-power-cmos-design-hardback-9780780334298","title":"Low-Power CMOS Design (Hardback) 9780780334298","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eLow-Power CMOS Design\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eAnantha Chandrakasan (Edited by), A Chandrakasan (Author), Robert W. Brodersen (Edited by)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780780334298, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 28 January 1998\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e656 pages\u003cbr\u003e28.6 x 22.2 x 3.8 cm, 1.694 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eThis collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003ePreface.  \u003cp\u003eOVERVIEW.\u003c\/p\u003e \u003cp\u003eLow Power Microelectronics: Retrospect and Prospect (J. Meindl).\u003c\/p\u003e \u003cp\u003eMicropower IC (E. Vittoz).\u003c\/p\u003e \u003cp\u003eLow-Power CMOS Digital Design (A. Chandrakasan, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eCMOS Scaling for High Performance and Low-Power—The Next Ten Years (B. Davari, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eLOW VOLTAGE TECHNOLOGIES AND CIRCUITS.\u003c\/p\u003e \u003cp\u003eLow-Voltage Technologies and Circuits (T. Kuroda \u0026amp; T. Sakurai).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eThreshold Voltage Scaling and Control.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIon-Implanted Complementary MOS Transistors in Low-Voltage Circuits (R. Swanson \u0026amp; J. Meindl).\u003c\/p\u003e \u003cp\u003eTrading Speed for Low Power by Choice of Supply and Threshold Voltages (D. Liu \u0026amp; C. Svensson).\u003c\/p\u003e \u003cp\u003eLimitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation (S. Sun \u0026amp; P. Tsui).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eMultiple Threshold CMOS (MTCMOS).\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS (S. Mutoh, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application (S. Mutoh, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSubstrate Bias Controlled Variable Threshold CMOS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit (K. Seta, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA 0.9V, 150MHz 10mW 4mm\u003csup\u003e2\u003c\/sup\u003e, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme (T. Kuroda, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSilicon-on-Insulator Based Technologies.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eSOI CMOS for Low Power Systems (D. Antoniadis).\u003c\/p\u003e \u003cp\u003eBack Gated CMOS on SOIAS for Dynamic Threshold Voltage Control (I. Yang, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eDesign of Low Power CMOS\/SOI Devices and Circuits for Memory and Signal Processing Applications (L. Thon \u0026amp; G. Shahidi).\u003c\/p\u003e \u003cp\u003eA Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation (F. Assaderaghi, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate (T. Douseki, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eEFFICIENT DC-DC CONVERSION AND ADAPTIVE POWER SUPPLY SYSTEMS.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eEfficient Low Voltage DC-DC Converter Design.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System (A. Stratakos, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eUltra Low-Power Control Circuits for PWM Converters (A. Dancy \u0026amp; A. Chandrakasan).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAdaptive Power Supply Systems.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA Voltage Reduction Technique for Battery Operated Systems (V. von Kaenel, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAutomatic Adjustment of Threshold and Supply Voltage for Minimum Power Consumption in CMOS Digital Circuits (V. von Kaenel, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eLow-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage (L. Nielsen, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Low-Power Switching Power Supply for Self-Clocked Systems (G. Wei \u0026amp; M. Horowitz).\u003c\/p\u003e \u003cp\u003eVariable-Voltage Digital-Signal Processing (V. Gutnik \u0026amp; A. Chandrakasan).\u003c\/p\u003e \u003cp\u003eScheduling for Reduced CPU Energy (M. Weiser, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eCIRCUIT AND LOGIC STYLES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eConventional Circuit and Logic Styles.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eSilicon-Gate CMOS Frequency Divider for the Electronic Wrist Watch (E. Vittoz, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eCODYMOS Frequency Dividers Achieve Low Power Consumption and High Frequency (H. Oguey \u0026amp; E. Vittoz).\u003c\/p\u003e \u003cp\u003eShort-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits (H. Veendrick).\u003c\/p\u003e \u003cp\u003eA 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic (K. Yano, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications (A. Parameswar, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eStatic Power Driven Voltage Scaling and Delay Driven Buffer Sizing in Mixed Swing QuadRail for Sub-IV I\/O Swings (R. Krishnamurthy, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eThe Power Consumption of CMOS Adders and Multiliers (T. Callaway \u0026amp; E. Swartzlander, Jr.).\u003c\/p\u003e \u003cp\u003eDelay Balanced Multipliers for Low Power\/Low Voltage DSP Core (T. Sakuta, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAsynchronous Does Not Imply Low Power, But, ... (K. Van Berkel, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eLatches and Flip-Flops for Low-Power Systems (C. Svensson \u0026amp; J. Yuan).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAdiabatic Logic Circuits.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eZig-Zag Path to Understanding (R. Landauer).\u003c\/p\u003e \u003cp\u003eA Low-Power Multiphase Circuit Technique (B. Watkins).\u003c\/p\u003e \u003cp\u003eAsymptotically Zero Energy Split-Level Charge Recovery Logic (S. Younis \u0026amp; T. Knight).\u003c\/p\u003e \u003cp\u003eLow Power Ditigal Systems Based on Adiabatic Switching Principles (W. Athas, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAdiabatic Dynamic Logic (A. Dickinson \u0026amp; J. Denker).\u003c\/p\u003e \u003cp\u003eDRIVING INTERCONNECT.\u003c\/p\u003e \u003cp\u003eSub-1-V Swin Internal Bus Architecture for Future Low-Power ULSIs (Y. Nakagome, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eData-Dependent Logic Swing Internal Bus Architecture for Ultra Low-Power LSIs (M. Hiraki, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAn Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSIs (H. Yamauchi, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eBus-Invert Coding for Low Power I\/O (M. Stan \u0026amp; W. Burleson).\u003c\/p\u003e \u003cp\u003eA Sub-CV\u003csup\u003e2\u003c\/sup\u003e Pad Driver with 10 ns Transition Time (L. Svensson, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eMEMORY CIRCUITS.\u003c\/p\u003e \u003cp\u003eReviews and Prospects of Low-Power Memory Circuits (K. Itoh).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eDRAM.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eTrends in Low-Power RAM Circuit Technologies (K. Itoh, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eStandby\/Active Mode Logic for Sub-1V Operating ULSI Memory (D. Takashima, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Charge Recycle Refresh for Gb-scale DRAM's in File Application (T. Kawahara, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSRAM.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA 1-V 1-Mb SRAM for Portable Equipment (H. Morimura \u0026amp; N. Shibata).\u003c\/p\u003e \u003cp\u003eA Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAMs (M. Ukita, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eTechniques to Reduce Power in Fast Wide Memories (B. Amrutur \u0026amp; M. Horowitz).\u003c\/p\u003e \u003cp\u003eA 2-ns, 5-mW, Synchronous-Powered Static-Circuit Associative TLB (H. Higuchi, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eDriving Source-Line (DSL) Cell Architecture for Sub-1-V High Speed Low Power Applications (H. Mizuno \u0026amp; T Nagano).\u003c\/p\u003e \u003cp\u003ePORTABLE TERMINAL ELECTRONICS.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eGeneral Purpose Processor Design.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eEnergy Dissipation in General Purpose Microprocessors (R. Gonzalez \u0026amp; M. Horowitz).\u003c\/p\u003e \u003cp\u003eEnergy Efficient CMOS Microprocessor Design (T. Burd \u0026amp; R. Brodersen).\u003c\/p\u003e \u003cp\u003eA 160MHz 32b 0.5W CMOS RISC Microprocessor (J. Montanaro, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA 320MHz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation (V. Von Kaenel, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e\u003cb\u003eDedicated and Programmable Digital Signal Processors.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA Low-Power Chipset for a Portable Multimedia I\/O Terminal (A. Chandrakasan, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Portable Real-Time Video Decoder for Wireless Communication (T. Meng, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eLow Power Design of Memory Intensive Functions (D. Lidsky \u0026amp; J. Rabaey).\u003c\/p\u003e \u003cp\u003eA 16b Low-Power Digital Signal Processor (K. Ueda, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA 1.8V 36mW DSP for the Half-Rate Speech CODEC (T. Shiraishi, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eDesign of a 1-V Programmable DSP for Wireless Communication (P. Landman, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eStage-Skip Pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer (M. Hiraki, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eCOMPUTER AIDED DESIGN TOOLS.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePower Analysis Techniques.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eTransition Density: A New Measure of Activity in Digital Circuits (E. Najm).\u003c\/p\u003e \u003cp\u003eEstimation of Average Switching Activity in Combinational and Sequential Circuits (A. Ghosh, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003ePower Estimation for Sequential Logic Circuits (C. Tsui, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Monte Carlo Approach for Power Estimation (R. Burch, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eStratified Random Sampling for Power Estimation (C.-S. Ding, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Survey of High-Level Power Estimation Techniques (P. Landman).\u003c\/p\u003e \u003cp\u003eActivity-Sensitive Architectural Power Analysis (P. Landman \u0026amp; J. Rabaey).\u003c\/p\u003e \u003cp\u003ePower Analysis of Embedded Software: A First Step Towards Software Power Minimization (V. Tiwari, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePower Optimization Techniques.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eTechnology Mapping for Low Power (V. Tiwari, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003ePOSE: Power Optimization and Synthesis Environment (S. Iman \u0026amp; M. Pedram).\u003c\/p\u003e \u003cp\u003eTransformation and Synthesis of FSMs fo Low-Power Gated-Clock Implementation (L. Benini \u0026amp; G. De Micheli).\u003c\/p\u003e \u003cp\u003ePrecomputation-Based Sequential Logic Optimization for Low Power (M. Alidina, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eGlitch Analysis and Reduction in Register Transfer Level Power Optimization (A. Raghunathan, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eExploiting Locality for Low-Power Design (R. Mehra, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eHYPER-LP: A System for Power Minimization Using Architectural Transformations (A. Chandrakasan, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eVariable Voltage Scheduling (S. Raje \u0026amp; M. Sarrafzadeh).\u003c\/p\u003e \u003cp\u003eSystem)-Level Transformations for Low Power Data Transfer and Storage (F. Catthoor, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAuthor Index.\u003c\/p\u003e \u003cp\u003eIndex.\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52407355834648,"sku":"9780780334298","price":157.98,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780780334298.jpg?v=1784164255","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/low-power-cmos-design-hardback-9780780334298","provider":"Freshly Printed Books","version":"1.0","type":"link"}