{"product_id":"fpga-prototyping-by-vhdl-examples-xilinx-microblaze-mcs-soc-hardback-9781119282747","title":"FPGA Prototyping by VHDL Examples; Xilinx MicroBlaze MCS SoC (Hardback) 9781119282747","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eFPGA Prototyping by VHDL Examples\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eXilinx MicroBlaze MCS SoC\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003ePong P. Chu (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781119282747, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 29 December 2017\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e632 pages\u003cbr\u003e25.6 x 18 x 3.8 cm, 1.27 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eA hands-on introduction to FPGA prototyping and SoC design\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eThis \u003ci\u003eSecond Edition\u003c\/i\u003e of the popular book follows the same “learning-by-doing” approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I\/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.\u003c\/p\u003e \u003cp\u003eThe new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The revised edition:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eAdds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.\u003c\/li\u003e \u003cli\u003eIntroduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.\u003c\/li\u003e \u003cli\u003eExpands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.\u003c\/li\u003e \u003cli\u003eIntroduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.\u003c\/li\u003e \u003cli\u003eProvides an overview of bus interconnect and interface circuit.\u003c\/li\u003e \u003cli\u003eIntroduces basic embedded system software development.\u003c\/li\u003e \u003cli\u003eSuggests additional modules and peripherals for interesting and challenging projects.\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eThe \u003ci\u003eFPGA Prototyping by VHDL Examples, Second Edition\u003c\/i\u003e makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003ePreface ix\u003c\/p\u003e \u003cp\u003eAcknowledgments xv\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART I BASIC  DIGITAL  CIRCUITS DEVELOPMENT\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Gate-level Combinational Circuit 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Overview of VHDL 1\u003c\/p\u003e \u003cp\u003e1.2 General description 2\u003c\/p\u003e \u003cp\u003e1.3 Structural description 6\u003c\/p\u003e \u003cp\u003e1.4 Top-level  signal mapping 8\u003c\/p\u003e \u003cp\u003e1.5 Testbench 9\u003c\/p\u003e \u003cp\u003e1.6 Bibliographic notes 11\u003c\/p\u003e \u003cp\u003e1.7 Suggested experiments 11\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Overview of FPGA and EDA  software 13\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 FPGA 13\u003c\/p\u003e \u003cp\u003e2.2 Overview of the Digilent Nexys  4 DDR    board 15\u003c\/p\u003e \u003cp\u003e2.3 Development flow 16\u003c\/p\u003e \u003cp\u003e2.4 Xilinx  Vivado  Design  Suite 18\u003c\/p\u003e \u003cp\u003e2.5 Bibliographic notes 18\u003c\/p\u003e \u003cp\u003e2.6 Suggested experiments 18\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 RT-level combinational circuit 23\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 RT-level components 23\u003c\/p\u003e \u003cp\u003e3.2 Routing circuit with concurrent assignment   statements 29\u003c\/p\u003e \u003cp\u003e3.3 Modeling with a  process 34\u003c\/p\u003e \u003cp\u003e3.4 Routing circuit with if and case    statements 36\u003c\/p\u003e \u003cp\u003e3.5 Constants and generics 41\u003c\/p\u003e \u003cp\u003e3.6 Replicated structure 44\u003c\/p\u003e \u003cp\u003e3.7 Design examples 46\u003c\/p\u003e \u003cp\u003e3.8 Bibliographic notes 58\u003c\/p\u003e \u003cp\u003e3.9 Suggested experiments 58\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Regular Sequential Circuit 61\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction 61\u003c\/p\u003e \u003cp\u003e4.2 HDL code of the FF and  register 64\u003c\/p\u003e \u003cp\u003e4.3 Simple design examples 67\u003c\/p\u003e \u003cp\u003e4.4 Testbench for sequential circuits 72\u003c\/p\u003e \u003cp\u003e4.5 Case study 75\u003c\/p\u003e \u003cp\u003e4.6 Timing  and clocking 87\u003c\/p\u003e \u003cp\u003e4.7 Bibliographic notes 90\u003c\/p\u003e \u003cp\u003e4.8 Suggested experiments 90\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 FSM  93\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 93\u003c\/p\u003e \u003cp\u003e5.2 FSM code development 97\u003c\/p\u003e \u003cp\u003e5.3 Design examples 100\u003c\/p\u003e \u003cp\u003e5.4 Bibliographic notes 110\u003c\/p\u003e \u003cp\u003e5.5 Suggested experiments 110\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 FSMD 113\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 113\u003c\/p\u003e \u003cp\u003e6.2 Code development of an FSMD 119\u003c\/p\u003e \u003cp\u003e6.3 Design examples 125\u003c\/p\u003e \u003cp\u003e6.4 Bibliographic notes 140\u003c\/p\u003e \u003cp\u003e6.5 Suggested experiments 141\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 RAM and Buffer of FPGA 145\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Embedded memory of FPGA device 145\u003c\/p\u003e \u003cp\u003e7.2 General description for RAM-like   component  147\u003c\/p\u003e \u003cp\u003e7.3 FIFO buffer  153\u003c\/p\u003e \u003cp\u003e7.4 HDL templates for memory  inference  158\u003c\/p\u003e \u003cp\u003e7.5 Overview of memory controller  164\u003c\/p\u003e \u003cp\u003e7.6 Bibliographic notes  166\u003c\/p\u003e \u003cp\u003e7.7 Suggested experiments  166\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART II EMBEDDED SOC I: VANILLA  FPRO SYSTEM\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Overview of Embedded SoC Systems 171\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Embedded  SoC 171\u003c\/p\u003e \u003cp\u003e8.2 Development Flow of Embedded   SoC 173\u003c\/p\u003e \u003cp\u003e8.3 FPro  SoC Platform 176\u003c\/p\u003e \u003cp\u003e8.4 Adaption  on  Digilent  Nexys  4  DDR board 180\u003c\/p\u003e \u003cp\u003e8.5 Portability 182\u003c\/p\u003e \u003cp\u003e8.6 Organization 184\u003c\/p\u003e \u003cp\u003e8.7 Bibliographic notes 184\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Bare Metal System Software Development 187\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Bare metal system development overview 187\u003c\/p\u003e \u003cp\u003e9.2 Memory-mapped  I\/O 189\u003c\/p\u003e \u003cp\u003e9.3 Direct  I\/O  Register Access 191\u003c\/p\u003e \u003cp\u003e9.4 Robust  I\/O  Register Access 193\u003c\/p\u003e \u003cp\u003e9.5 Techniques for low-level I\/O  operations 197\u003c\/p\u003e \u003cp\u003e9.6 Device Drivers 199\u003c\/p\u003e \u003cp\u003e9.7 FPro  Utility  Routines  and  Directory Structure 204\u003c\/p\u003e \u003cp\u003e9.8 Test program 208\u003c\/p\u003e \u003cp\u003e9.9 Bibliographic notes 211\u003c\/p\u003e \u003cp\u003e9.10 Suggested experiments 211\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 FPro Bus Protocol and MMIO Slot Specification 213\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 FPro Bus 213\u003c\/p\u003e \u003cp\u003e10.2 Interface with bus 216\u003c\/p\u003e \u003cp\u003e10.3 MMIO I\/O core 222\u003c\/p\u003e \u003cp\u003e10.4 Timer core development 226\u003c\/p\u003e \u003cp\u003e10.5 MMIO controller 229\u003c\/p\u003e \u003cp\u003e10.6 MCS I\/O bus and bridge 234\u003c\/p\u003e \u003cp\u003e10.7 Vanilla FPRO System Construction 238\u003c\/p\u003e \u003cp\u003e10.8 Bibliographic notes 240\u003c\/p\u003e \u003cp\u003e10.9 Suggested experiments 240\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 UART Core 243\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 243\u003c\/p\u003e \u003cp\u003e11.2 UART Construction 245\u003c\/p\u003e \u003cp\u003e11.3 UART core  development 253\u003c\/p\u003e \u003cp\u003e11.4 UART driver 256\u003c\/p\u003e \u003cp\u003e11.5   Additional  Project Ideas 262\u003c\/p\u003e \u003cp\u003e11.6 Bibliographic notes 265\u003c\/p\u003e \u003cp\u003e11.7 Suggested experiments 266\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART III EMBEDDED SOC II: BASIC I\/O CORES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Xilinx XADC Core 271\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Overview of XADC 271\u003c\/p\u003e \u003cp\u003e12.2 XADC core development 273\u003c\/p\u003e \u003cp\u003e12.3 XADC core device driver 278\u003c\/p\u003e \u003cp\u003e12.4 Sampler FPro System 281\u003c\/p\u003e \u003cp\u003e12.5 Additional Project Ideas 291\u003c\/p\u003e \u003cp\u003e12.6 Bibliographic notes 292\u003c\/p\u003e \u003cp\u003e12.7 Suggested experiments 292\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Pulse Width Modulation Core 295\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Introduction 295\u003c\/p\u003e \u003cp\u003e13.2 PWM Design 296\u003c\/p\u003e \u003cp\u003e13.3 PWM core development 299\u003c\/p\u003e \u003cp\u003e13.4 PWM  driver 302\u003c\/p\u003e \u003cp\u003e13.5 Testing 303\u003c\/p\u003e \u003cp\u003e13.6 Project ideas 304\u003c\/p\u003e \u003cp\u003e13.7 Suggested experiments 305\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Debouncing  core and LED-Mux  Core 307\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Debouncing Core 307\u003c\/p\u003e \u003cp\u003e14.2 LED-Mux   Core 313\u003c\/p\u003e \u003cp\u003e14.3 Project  Ideas 319\u003c\/p\u003e \u003cp\u003e14.4 Suggested Experiments 320\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 SPI Core 323\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Overview 323\u003c\/p\u003e \u003cp\u003e15.3 SPI  Core Development  333\u003c\/p\u003e \u003cp\u003e15.4 SPI Driver  336\u003c\/p\u003e \u003cp\u003e15.5 Test  338\u003c\/p\u003e \u003cp\u003e15.6 Project Ideas  341\u003c\/p\u003e \u003cp\u003e15.7 Bibliographic notes  342\u003c\/p\u003e \u003cp\u003e15.8 Suggested Experiments  342\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 I2C Core 347\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Overview 347\u003c\/p\u003e \u003cp\u003e16.2 I2C Controller 350\u003c\/p\u003e \u003cp\u003e16.3 I2C Core Development 360\u003c\/p\u003e \u003cp\u003e16.4 I2C  Driver 361\u003c\/p\u003e \u003cp\u003e16.5 Test 365\u003c\/p\u003e \u003cp\u003e16.6 Project  Idea 366\u003c\/p\u003e \u003cp\u003e16.7 Bibliographic notes 367\u003c\/p\u003e \u003cp\u003e16.8 Suggested experiments 367\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 PS2 Core 371\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Introduction 371\u003c\/p\u003e \u003cp\u003e17.2 PS2 Controller 373\u003c\/p\u003e \u003cp\u003e17.3 PS2 core development 383\u003c\/p\u003e \u003cp\u003e17.4 PS2 driver 384\u003c\/p\u003e \u003cp\u003e17.5 Test 393\u003c\/p\u003e \u003cp\u003e17.6 Bibliographic notes 394\u003c\/p\u003e \u003cp\u003e17.7 Suggested experiments 394\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 Sound I: DDFS  Core 397\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Introduction 397\u003c\/p\u003e \u003cp\u003e18.2 Design and implementation 397\u003c\/p\u003e \u003cp\u003e18.3 Fixed-point arithmetic 400\u003c\/p\u003e \u003cp\u003e18.4 DDFS Construction 402\u003c\/p\u003e \u003cp\u003e18.5 DAC (digital-to-analog converter) 404\u003c\/p\u003e \u003cp\u003e18.6 DDFS core development 407\u003c\/p\u003e \u003cp\u003e18.7 DDFS driver 409\u003c\/p\u003e \u003cp\u003e18.8 Testing 412\u003c\/p\u003e \u003cp\u003e18.9 Bibliographic notes 413\u003c\/p\u003e \u003cp\u003e18.10 Suggested experiments 413\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 Sound II: ADSR Core 415\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Introduction 415\u003c\/p\u003e \u003cp\u003e19.2 ADSR envelope generator 416\u003c\/p\u003e \u003cp\u003e19.3 ADSR core development 421\u003c\/p\u003e \u003cp\u003e19.4 ADRS driver 423\u003c\/p\u003e \u003cp\u003e19.5 Testing 429\u003c\/p\u003e \u003cp\u003e19.6 Project  Idea 430\u003c\/p\u003e \u003cp\u003e19.7 Bibliographic notes 431\u003c\/p\u003e \u003cp\u003e19.8 Suggested experiments 431\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART IV EMBEDDED SOC III: VIDEO  CORES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e20 Introduction to Video System 435\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e20.1 Introduction to a video  display 435\u003c\/p\u003e \u003cp\u003e20.2 Stream interface 437\u003c\/p\u003e \u003cp\u003e20.3 VGA Synchronization 439\u003c\/p\u003e \u003cp\u003e20.4 Bar  test-pattern generator 448\u003c\/p\u003e \u003cp\u003e20.5 Color-to-grayscale conversion circuit 449\u003c\/p\u003e \u003cp\u003e20.6 Demo video system 451\u003c\/p\u003e \u003cp\u003e20.7 Advanced video standards 452\u003c\/p\u003e \u003cp\u003e20.8 Bibliographic notes 453\u003c\/p\u003e \u003cp\u003e20.9 Suggested experiments 454\u003c\/p\u003e \u003cp\u003e\u003cb\u003e21 FPro Video Subsystem 457\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e21.1 Organization of video subsystem 457\u003c\/p\u003e \u003cp\u003e21.2 FPro video IP core 461\u003c\/p\u003e \u003cp\u003e21.3 Example video cores 466\u003c\/p\u003e \u003cp\u003e21.4 FPro video synchronization core 470\u003c\/p\u003e \u003cp\u003e21.5 Daisy video subsystem 479\u003c\/p\u003e \u003cp\u003e21.6 Vanilla daisy FPro system 486\u003c\/p\u003e \u003cp\u003e21.7 Video driver and testing program 490\u003c\/p\u003e \u003cp\u003e21.8 Bibliographic notes 493\u003c\/p\u003e \u003cp\u003e21.9 Suggested experiments 493\u003c\/p\u003e \u003cp\u003e\u003cb\u003e22 Sprite Core 497\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e22.1 Introduction 497\u003c\/p\u003e \u003cp\u003e22.2 Basic design 498\u003c\/p\u003e \u003cp\u003e22.3 Mouse pointer core 500\u003c\/p\u003e \u003cp\u003e22.4 “Ghost” character core 505\u003c\/p\u003e \u003cp\u003e22.5 Sprite core driver and testing program 513\u003c\/p\u003e \u003cp\u003e22.6 Bibliographic notes 516\u003c\/p\u003e \u003cp\u003e22.7 Suggested experiments 516\u003c\/p\u003e \u003cp\u003e\u003cb\u003e23 On-Screen-Display Core 519\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e23.1 Introduction to tile graphics 519\u003c\/p\u003e \u003cp\u003e23.2 Basic OSD design 521\u003c\/p\u003e \u003cp\u003e23.3 OSD core  524\u003c\/p\u003e \u003cp\u003e23.4 OSD core driver and testing   program  530\u003c\/p\u003e \u003cp\u003e23.5 Bibliographic notes  532\u003c\/p\u003e \u003cp\u003e23.6 Suggested experiments  532\u003c\/p\u003e \u003cp\u003e\u003cb\u003e24 VGA  Frame  Buffer Core 535\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e24.1 Overview 535\u003c\/p\u003e \u003cp\u003e24.2 Frame buffer core 536\u003c\/p\u003e \u003cp\u003e24.3 Register map 540\u003c\/p\u003e \u003cp\u003e24.4 Driver and testing program 542 543\u003c\/p\u003e \u003cp\u003e24.5 Project Ideas 545\u003c\/p\u003e \u003cp\u003e24.6 Bibliographic notes 547\u003c\/p\u003e \u003cp\u003e24.7 Suggested experiments 547\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART V EPILOGUE\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e25  What Next 553\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 557\u003c\/p\u003e \u003cp\u003eAppendix A: Tutorials 561\u003c\/p\u003e \u003cp\u003eA.1 Overview of Xilinx Vivado  IDE 561\u003c\/p\u003e \u003cp\u003eA.2 Short tutorial on Vivado hardware   development 565\u003c\/p\u003e \u003cp\u003eA.3 Short tutorial on Vivado   simulation 570\u003c\/p\u003e \u003cp\u003eA.4 Tutorial on IP instantiation 574\u003c\/p\u003e \u003cp\u003eA.5 Short tutorial on FPro system   development 580\u003c\/p\u003e \u003cp\u003eA.6 Bibliographic notes 587\u003c\/p\u003e \u003cp\u003eTopic Index 589\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley","offers":[{"title":"Brand New","offer_id":52458382164248,"sku":"9781119282747","price":84.55,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781119282747.jpg?v=1785372035","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/fpga-prototyping-by-vhdl-examples-xilinx-microblaze-mcs-soc-hardback-9781119282747","provider":"Freshly Printed Books","version":"1.0","type":"link"}