{"product_id":"fpga-prototyping-by-systemverilog-examples-xilinx-microblaze-mcs-soc-edition-hardback-9781119282662","title":"FPGA Prototyping by SystemVerilog Examples; Xilinx MicroBlaze MCS SoC Edition (Hardback) 9781119282662","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eFPGA Prototyping by SystemVerilog Examples\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eXilinx MicroBlaze MCS SoC Edition\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003ePong P. Chu (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781119282662, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 29 June 2018\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e656 pages\u003cbr\u003e25.6 x 18.3 x 3.6 cm, 1.52 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eA hands-on introduction to FPGA prototyping and SoC design\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eThis is the successor edition of the popular \u003ci\u003eFPGA Prototyping by Verilog Examples\u003c\/i\u003e text. It follows the same “learning-by-doing” approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I\/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems.\u003c\/p\u003e \u003cp\u003eThe book is completely updated and uses the SystemVerilog language, which “absorbs” the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The new edition:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eAdds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.\u003c\/li\u003e \u003cli\u003eIntroduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.\u003c\/li\u003e \u003cli\u003eExpands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.\u003c\/li\u003e \u003cli\u003eProvides a detailed discussion on blocking and nonblocking statements and coding styles.\u003c\/li\u003e \u003cli\u003eDescribes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.\u003c\/li\u003e \u003cli\u003eProvides an overview of bus interconnect and interface circuit.\u003c\/li\u003e \u003cli\u003ePresents basic embedded system software development.\u003c\/li\u003e \u003cli\u003eSuggests additional modules and peripherals for interesting and challenging projects.\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eFPGA Prototyping by SystemVerilog Examples\u003c\/i\u003e makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003ePreface xxvii\u003c\/p\u003e \u003cp\u003eAcknowledgments xxxiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART I BASIC DIGITAL CIRCUITS DEVELOPMENT\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Gate-Level Combinational Circuit 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Introduction 1\u003c\/p\u003e \u003cp\u003e1.1.1 Brief history of Verilog and SystemVerilog 1\u003c\/p\u003e \u003cp\u003e1.1.2 Book coverage 2\u003c\/p\u003e \u003cp\u003e1.2 General description 3\u003c\/p\u003e \u003cp\u003e1.3 Basic lexical elements and data types 4\u003c\/p\u003e \u003cp\u003e1.3.1 Lexical elements 4\u003c\/p\u003e \u003cp\u003e1.3.2 Data types used in the book 5\u003c\/p\u003e \u003cp\u003e1.3.3 Number representation 6\u003c\/p\u003e \u003cp\u003e1.3.4 Operators 7\u003c\/p\u003e \u003cp\u003e1.4 Program skeleton 7\u003c\/p\u003e \u003cp\u003e1.4.1 Port declaration 7\u003c\/p\u003e \u003cp\u003e1.4.2 Signal declaration 8\u003c\/p\u003e \u003cp\u003e1.4.3 Program body 8\u003c\/p\u003e \u003cp\u003e1.4.4 Concurrent semantics 9\u003c\/p\u003e \u003cp\u003e1.4.5 Another example 10\u003c\/p\u003e \u003cp\u003e1.5 Structural description 10\u003c\/p\u003e \u003cp\u003e1.6 Top-level signal mapping 13\u003c\/p\u003e \u003cp\u003e1.7 Testbench 14\u003c\/p\u003e \u003cp\u003e1.8 Bibliographic notes 16\u003c\/p\u003e \u003cp\u003e1.9 Suggested experiments 16\u003c\/p\u003e \u003cp\u003e1.9.1 Code for gate-level greater-than circuit 17\u003c\/p\u003e \u003cp\u003e1.9.2 Code for gate-level binary decoder 17\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Overview of FPGA and EDA Software 19\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 FPGA 19\u003c\/p\u003e \u003cp\u003e2.1.1 Overview of a general FPGA device 19\u003c\/p\u003e \u003cp\u003e2.1.2 Overview of the Xilinx Artix-7 devices 20\u003c\/p\u003e \u003cp\u003e2.2 Overview of the Digilent Nexys 4 DDR board 21\u003c\/p\u003e \u003cp\u003e2.3 Development flow 22\u003c\/p\u003e \u003cp\u003e2.4 Xilinx Vivado Design Suite 24\u003c\/p\u003e \u003cp\u003e2.5 Bibliographic notes 24\u003c\/p\u003e \u003cp\u003e2.6 Suggested experiments 24\u003c\/p\u003e \u003cp\u003e2.6.1 Gate-level greater-than circuit 24\u003c\/p\u003e \u003cp\u003e2.6.2 Gate-level binary decoder 26\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 RT-Level Combinational Circuit 29\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Operators 29\u003c\/p\u003e \u003cp\u003e3.1.1 Arithmetic operators 31\u003c\/p\u003e \u003cp\u003e3.1.2 Shift operators 31\u003c\/p\u003e \u003cp\u003e3.1.3 Relational and equality operators 32\u003c\/p\u003e \u003cp\u003e3.1.4 Bitwise, reduction, and logical operators 32\u003c\/p\u003e \u003cp\u003e3.1.5 Concatenation and replication operators 33\u003c\/p\u003e \u003cp\u003e3.1.6 Conditional operators 34\u003c\/p\u003e \u003cp\u003e3.1.7 Operator precedence 35\u003c\/p\u003e \u003cp\u003e3.1.8 Expression bit-length adjustment 35\u003c\/p\u003e \u003cp\u003e3.1.9 Synthesis of z and x values 36\u003c\/p\u003e \u003cp\u003e3.2 Always block for a combinational circuit 38\u003c\/p\u003e \u003cp\u003e3.2.1 Overview of always block 39\u003c\/p\u003e \u003cp\u003e3.2.2 Procedural assignment 40\u003c\/p\u003e \u003cp\u003e3.2.3 Conceptual examples 40\u003c\/p\u003e \u003cp\u003e3.3 Coding guidelines 43\u003c\/p\u003e \u003cp\u003e3.4 If statement 43\u003c\/p\u003e \u003cp\u003e3.4.1 Syntax 43\u003c\/p\u003e \u003cp\u003e3.4.2 Examples 44\u003c\/p\u003e \u003cp\u003e3.5 Case statement 45\u003c\/p\u003e \u003cp\u003e3.5.1 Syntax 45\u003c\/p\u003e \u003cp\u003e3.5.2 Examples 46\u003c\/p\u003e \u003cp\u003e3.5.3 The casez and casex statements 47\u003c\/p\u003e \u003cp\u003e3.5.4 Full case and parallel case 48\u003c\/p\u003e \u003cp\u003e3.6 Routing structure of conditional control constructs 49\u003c\/p\u003e \u003cp\u003e3.6.1 Priority routing network 49\u003c\/p\u003e \u003cp\u003e3.6.2 Multiplexing network 51\u003c\/p\u003e \u003cp\u003e3.7 Additional coding guidelines for an always block 52\u003c\/p\u003e \u003cp\u003e3.7.1 Common errors in combinational circuit codes 52\u003c\/p\u003e \u003cp\u003e3.7.2 Guidelines 56\u003c\/p\u003e \u003cp\u003e3.8 Parameter and constant 56\u003c\/p\u003e \u003cp\u003e3.8.1 Constant 56\u003c\/p\u003e \u003cp\u003e3.8.2 Parameter 58\u003c\/p\u003e \u003cp\u003e3.9 Replicated structure 59\u003c\/p\u003e \u003cp\u003e3.9.1 Generate-for statement 59\u003c\/p\u003e \u003cp\u003e3.9.2 Procedural-for statement 60\u003c\/p\u003e \u003cp\u003e3.9.3 Example 60\u003c\/p\u003e \u003cp\u003e3.10 Design examples 62\u003c\/p\u003e \u003cp\u003e3.10.1 Hexadecimal digit to seven-segment LED decoder 62\u003c\/p\u003e \u003cp\u003e3.10.2 Sign-magnitude adder 65\u003c\/p\u003e \u003cp\u003e3.10.3 Barrel shifter 68\u003c\/p\u003e \u003cp\u003e3.10.4 Simplified floating-point adder 69\u003c\/p\u003e \u003cp\u003e3.11 Bibliographic notes 73\u003c\/p\u003e \u003cp\u003e3.12 Suggested experiments 73\u003c\/p\u003e \u003cp\u003e3.12.1 Multi-function barrel shifter 73\u003c\/p\u003e \u003cp\u003e3.12.2 Parameterized barrel shifter 74\u003c\/p\u003e \u003cp\u003e3.12.3 Dual-priority encoder 74\u003c\/p\u003e \u003cp\u003e3.12.4 BCD incrementor 74\u003c\/p\u003e \u003cp\u003e3.12.5 Floating-point greater-than circuit 74\u003c\/p\u003e \u003cp\u003e3.12.6 Floating-point and signed integer conversion circuit 74\u003c\/p\u003e \u003cp\u003e3.12.7 Enhanced floating-point adder 75\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Regular Sequential Circuit 77\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction 77\u003c\/p\u003e \u003cp\u003e4.1.1 D FF and register 78\u003c\/p\u003e \u003cp\u003e4.1.2 Basic block system 78\u003c\/p\u003e \u003cp\u003e4.1.3 Code development 79\u003c\/p\u003e \u003cp\u003e4.1.4 Sequential circuit coding guidelines and style 79\u003c\/p\u003e \u003cp\u003e4.2 HDL code of the FF and register 80\u003c\/p\u003e \u003cp\u003e4.2.1 D FF 80\u003c\/p\u003e \u003cp\u003e4.2.2 Register 85\u003c\/p\u003e \u003cp\u003e4.3 Simple design examples 85\u003c\/p\u003e \u003cp\u003e4.3.1 Shift register 85\u003c\/p\u003e \u003cp\u003e4.3.2 Binary counter and variant 87\u003c\/p\u003e \u003cp\u003e4.4 Testbench for sequential circuits 89\u003c\/p\u003e \u003cp\u003e4.5 Case study 93\u003c\/p\u003e \u003cp\u003e4.5.1 LED time-multiplexing circuit 93\u003c\/p\u003e \u003cp\u003e4.5.2 Stopwatch 101\u003c\/p\u003e \u003cp\u003e4.6 Timing and clocking 104\u003c\/p\u003e \u003cp\u003e4.6.1 Timing of FF 104\u003c\/p\u003e \u003cp\u003e4.6.2 Maximum operating frequency 104\u003c\/p\u003e \u003cp\u003e4.6.3 Clock tree 107\u003c\/p\u003e \u003cp\u003e4.6.4 GALS system and CDC 107\u003c\/p\u003e \u003cp\u003e4.7 Bibliographic notes 108\u003c\/p\u003e \u003cp\u003e4.8 Suggested experiments 108\u003c\/p\u003e \u003cp\u003e4.8.1 Programmable square wave generator 108\u003c\/p\u003e \u003cp\u003e4.8.2 PWM and LED dimmer 108\u003c\/p\u003e \u003cp\u003e4.8.3 Rotating square circuit 109\u003c\/p\u003e \u003cp\u003e4.8.4 Heartbeat circuit 109\u003c\/p\u003e \u003cp\u003e4.8.5 Rotating LED banner circuit 109\u003c\/p\u003e \u003cp\u003e4.8.6 Enhanced stopwatch 110\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 FSM 111\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 111\u003c\/p\u003e \u003cp\u003e5.1.1 Mealy and Moore outputs 112\u003c\/p\u003e \u003cp\u003e5.1.2 FSM representation 112\u003c\/p\u003e \u003cp\u003e5.2 FSM code development 115\u003c\/p\u003e \u003cp\u003e5.2.1 Enumerated data type and state assignment 115\u003c\/p\u003e \u003cp\u003e5.2.2 Multi-segment code 116\u003c\/p\u003e \u003cp\u003e5.2.3 Two-segment code 117\u003c\/p\u003e \u003cp\u003e5.3 Design examples 118\u003c\/p\u003e \u003cp\u003e5.3.1 Rising-edge detector 118\u003c\/p\u003e \u003cp\u003e5.3.2 Debouncing circuit 123\u003c\/p\u003e \u003cp\u003e5.3.3 Testing circuit 126\u003c\/p\u003e \u003cp\u003e5.4 Bibliographic notes 128\u003c\/p\u003e \u003cp\u003e5.5 Suggested experiments 128\u003c\/p\u003e \u003cp\u003e5.5.1 Dual-edge detector 128\u003c\/p\u003e \u003cp\u003e5.5.2 Early detection debouncing circuit 128\u003c\/p\u003e \u003cp\u003e5.5.3 Parking lot occupancy counter 129\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 FSMD 131\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 131\u003c\/p\u003e \u003cp\u003e6.1.1 Single RT operation 132\u003c\/p\u003e \u003cp\u003e6.1.2 ASMD chart 132\u003c\/p\u003e \u003cp\u003e6.1.3 Decision box with a register 134\u003c\/p\u003e \u003cp\u003e6.2 Code development of an FSMD 137\u003c\/p\u003e \u003cp\u003e6.2.1 Debouncing circuit based on RT methodology 137\u003c\/p\u003e \u003cp\u003e6.2.2 Code with explicit data path components 137\u003c\/p\u003e \u003cp\u003e6.2.3 Code with implicit data path components 140\u003c\/p\u003e \u003cp\u003e6.2.4 Comparison 142\u003c\/p\u003e \u003cp\u003e6.3 Design examples 144\u003c\/p\u003e \u003cp\u003e6.3.1 Fibonacci number circuit 144\u003c\/p\u003e \u003cp\u003e6.3.2 Division circuit 147\u003c\/p\u003e \u003cp\u003e6.3.3 Binary-to-BCD conversion circuit 150\u003c\/p\u003e \u003cp\u003e6.3.4 Period counter 153\u003c\/p\u003e \u003cp\u003e6.3.5 Accurate low-frequency counter 156\u003c\/p\u003e \u003cp\u003e6.4 Bibliographic notes 159\u003c\/p\u003e \u003cp\u003e6.5 Suggested experiments 159\u003c\/p\u003e \u003cp\u003e6.5.1 Early detection debouncing circuit 159\u003c\/p\u003e \u003cp\u003e6.5.2 BCD-to-binary conversion circuit 160\u003c\/p\u003e \u003cp\u003e6.5.3 Fibonacci circuit with BCD I\/O: design approach 1 160\u003c\/p\u003e \u003cp\u003e6.5.4 Fibonacci circuit with BCD I\/O: design approach 2 160\u003c\/p\u003e \u003cp\u003e6.5.5 Auto-scaled low-frequency counter 161\u003c\/p\u003e \u003cp\u003e6.5.6 Reaction timer 161\u003c\/p\u003e \u003cp\u003e6.5.7 Babbage difference engine emulation circuit 162\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 RAM and Buffer of FPGA 165\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Embedded memory of FPGA device 165\u003c\/p\u003e \u003cp\u003e7.1.1 Memory of an Artix device 166\u003c\/p\u003e \u003cp\u003e7.1.2 Memory available in the Nexys 4 DDR board 166\u003c\/p\u003e \u003cp\u003e7.2 General description for a RAM-like component 167\u003c\/p\u003e \u003cp\u003e7.2.1 Register file 167\u003c\/p\u003e \u003cp\u003e7.2.2 Dynamic array indexing operation 169\u003c\/p\u003e \u003cp\u003e7.2.3 Key aspects of a RAM module 170\u003c\/p\u003e \u003cp\u003e7.2.4 Genuine ROM 171\u003c\/p\u003e \u003cp\u003e7.3 FIFO buffer 173\u003c\/p\u003e \u003cp\u003e7.3.1 FIFO read configuration 174\u003c\/p\u003e \u003cp\u003e7.3.2 Circular queue implementation 175\u003c\/p\u003e \u003cp\u003e7.4 HDL templates for memory inference 178\u003c\/p\u003e \u003cp\u003e7.4.1 Methods to incorporate memory modules 178\u003c\/p\u003e \u003cp\u003e7.4.2 Synchronous dual-port RAM 179\u003c\/p\u003e \u003cp\u003e7.4.3 “Simple” synchronous dual-port RAM 180\u003c\/p\u003e \u003cp\u003e7.4.4 Synchronous single-port RAM 181\u003c\/p\u003e \u003cp\u003e7.4.5 Synchronous ROM 182\u003c\/p\u003e \u003cp\u003e7.4.6 BRAM-based FIFO buffer 183\u003c\/p\u003e \u003cp\u003e7.4.7 Design considerations 183\u003c\/p\u003e \u003cp\u003e7.5 Overview of memory controller 184\u003c\/p\u003e \u003cp\u003e7.6 Bibliographic notes 185\u003c\/p\u003e \u003cp\u003e7.7 Suggested experiments 186\u003c\/p\u003e \u003cp\u003e7.7.1 ROM-based sign-magnitude adder 186\u003c\/p\u003e \u003cp\u003e7.7.2 ROM-based temperature conversion 186\u003c\/p\u003e \u003cp\u003e7.7.3 FIFO with data width conversion 186\u003c\/p\u003e \u003cp\u003e7.7.4 Standard FIFO to FWFT FIFO conversion circuit 187\u003c\/p\u003e \u003cp\u003e7.7.5 FIFO buffer with extended status 187\u003c\/p\u003e \u003cp\u003e7.7.6 Stack 187\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Selected Topics of SystemVerilog 189\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Timing model 189\u003c\/p\u003e \u003cp\u003e8.1.1 Concurrent constructs 190\u003c\/p\u003e \u003cp\u003e8.1.2 Assignment statement 190\u003c\/p\u003e \u003cp\u003e8.1.3 Basic model 190\u003c\/p\u003e \u003cp\u003e8.1.4 Blocking versus nonblocking assignment 192\u003c\/p\u003e \u003cp\u003e8.2 Coding guidelines revisited 194\u003c\/p\u003e \u003cp\u003e8.2.1 “Single variable assignment” guideline 195\u003c\/p\u003e \u003cp\u003e8.2.2 “Blocking assignment for combinational circuit” guideline 195\u003c\/p\u003e \u003cp\u003e8.2.3 “Nonblocking assignment for register” guideline 197\u003c\/p\u003e \u003cp\u003e8.3 Alternative coding style 198\u003c\/p\u003e \u003cp\u003e8.3.1 First coding style revisited 198\u003c\/p\u003e \u003cp\u003e8.3.2 Sequential circuit with mixed blocking and nonblocking assignments 199\u003c\/p\u003e \u003cp\u003e8.3.3 Combined coding style 201\u003c\/p\u003e \u003cp\u003e8.3.4 Summary 206\u003c\/p\u003e \u003cp\u003e8.4 Data types 206\u003c\/p\u003e \u003cp\u003e8.4.1 The net and variable types 206\u003c\/p\u003e \u003cp\u003e8.4.2 The logic data type 207\u003c\/p\u003e \u003cp\u003e8.4.3 Limitation of the logic data type 208\u003c\/p\u003e \u003cp\u003e8.4.4 New data types in SystemVerilog 208\u003c\/p\u003e \u003cp\u003e8.5 Use of the signed data type 209\u003c\/p\u003e \u003cp\u003e8.5.1 Overview 209\u003c\/p\u003e \u003cp\u003e8.5.2 Signed number conversion 210\u003c\/p\u003e \u003cp\u003e8.6 Bibliographic notes 211\u003c\/p\u003e \u003cp\u003e8.7 Suggested experiments 211\u003c\/p\u003e \u003cp\u003e8.7.1 Shift register with blocking and nonblocking assignments 211\u003c\/p\u003e \u003cp\u003e8.7.2 Alternative coding style for the BCD counter 212\u003c\/p\u003e \u003cp\u003e8.7.3 Alternative coding style for the FIFO buffer 212\u003c\/p\u003e \u003cp\u003e8.7.4 Alternative coding style for the Fibonacci circuit 212\u003c\/p\u003e \u003cp\u003e8.7.5 Dual-mode comparator 212\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART II EMBEDDED SOC I: VANILLA FPRO SYSTEM\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Overview of Embedded SoC Systems 215\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Embedded SoC 215\u003c\/p\u003e \u003cp\u003e9.1.1 Overview of embedded systems 215\u003c\/p\u003e \u003cp\u003e9.1.2 FPGA-based SoC 216\u003c\/p\u003e \u003cp\u003e9.1.3 IP cores 216\u003c\/p\u003e \u003cp\u003e9.2 Development flow of the embedded SoC 217\u003c\/p\u003e \u003cp\u003e9.2.1 Hardware–software partition 217\u003c\/p\u003e \u003cp\u003e9.2.2 Hardware development flow 217\u003c\/p\u003e \u003cp\u003e9.2.3 Software development flow 219\u003c\/p\u003e \u003cp\u003e9.2.4 Physical implementation and test 219\u003c\/p\u003e \u003cp\u003e9.2.5 Custom IP core development 219\u003c\/p\u003e \u003cp\u003e9.3 FPro SoC Platform 220\u003c\/p\u003e \u003cp\u003e9.3.1 Motivations 220\u003c\/p\u003e \u003cp\u003e9.3.2 Platform hardware organization 221\u003c\/p\u003e \u003cp\u003e9.3.3 Platform software organization 223\u003c\/p\u003e \u003cp\u003e9.3.4 Modified development flow 224\u003c\/p\u003e \u003cp\u003e9.4 Adaptation on the Digilent Nexys 4 DDR board 224\u003c\/p\u003e \u003cp\u003e9.5 Portability 226\u003c\/p\u003e \u003cp\u003e9.5.1 Processor Module and Bridge 226\u003c\/p\u003e \u003cp\u003e9.5.2 MMIO subsystem 227\u003c\/p\u003e \u003cp\u003e9.5.3 Video subsystem 227\u003c\/p\u003e \u003cp\u003e9.6 Organization 228\u003c\/p\u003e \u003cp\u003e9.7 Bibliographic notes 228\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Bare Metal System Software Development 231\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Bare metal system development overview 231\u003c\/p\u003e \u003cp\u003e10.1.1 Desktop-like system versus bare metal system 231\u003c\/p\u003e \u003cp\u003e10.1.2 Basic embedded program architecture 232\u003c\/p\u003e \u003cp\u003e10.2 Memory-mapped I\/O 233\u003c\/p\u003e \u003cp\u003e10.2.1 Overview 233\u003c\/p\u003e \u003cp\u003e10.2.2 Memory alignment 234\u003c\/p\u003e \u003cp\u003e10.2.3 I\/O register map 234\u003c\/p\u003e \u003cp\u003e10.2.4 I\/O address space of the FPro system 234\u003c\/p\u003e \u003cp\u003e10.3 Direct I\/O Register Access 235\u003c\/p\u003e \u003cp\u003e10.3.1 Review of C pointer 235\u003c\/p\u003e \u003cp\u003e10.3.2 C pointer for I\/O register 236\u003c\/p\u003e \u003cp\u003e10.4 Robust I\/O register access 237\u003c\/p\u003e \u003cp\u003e10.4.1 chu_io_map.h and chu_io_map.svh 237\u003c\/p\u003e \u003cp\u003e10.4.2 inttypes.h 238\u003c\/p\u003e \u003cp\u003e10.4.3 chu_io_rw.h 239\u003c\/p\u003e \u003cp\u003e10.5 Techniques for low-level I\/O operations 241\u003c\/p\u003e \u003cp\u003e10.5.1 Bit manipulation 241\u003c\/p\u003e \u003cp\u003e10.5.2 Packing and unpacking 242\u003c\/p\u003e \u003cp\u003e10.6 Device Drivers 243\u003c\/p\u003e \u003cp\u003e10.6.1 Overview 243\u003c\/p\u003e \u003cp\u003e10.6.2 GPO and GPI drivers 243\u003c\/p\u003e \u003cp\u003e10.6.3 Timer driver 245\u003c\/p\u003e \u003cp\u003e10.6.4 UART driver 247\u003c\/p\u003e \u003cp\u003e10.7 FPro utility routines and directory structure 248\u003c\/p\u003e \u003cp\u003e10.7.1 Minimal hardware requirements 248\u003c\/p\u003e \u003cp\u003e10.7.2 Utility routines 248\u003c\/p\u003e \u003cp\u003e10.7.3 Directory structure 251\u003c\/p\u003e \u003cp\u003e10.8 Test program 252\u003c\/p\u003e \u003cp\u003e10.8.1 IP core verification routine 252\u003c\/p\u003e \u003cp\u003e10.8.2 Programming with limited memory 252\u003c\/p\u003e \u003cp\u003e10.8.3 Test function integration 252\u003c\/p\u003e \u003cp\u003e10.8.4 Test program for the vanilla FPro system 253\u003c\/p\u003e \u003cp\u003e10.8.5 Implementation 254\u003c\/p\u003e \u003cp\u003e10.9 Bibliographic notes 255\u003c\/p\u003e \u003cp\u003e10.10 Suggested experiments 255\u003c\/p\u003e \u003cp\u003e10.10.1 Chasing LEDs 255\u003c\/p\u003e \u003cp\u003e10.10.2 Collision LEDs 256\u003c\/p\u003e \u003cp\u003e10.10.3 Pulse width modulation 256\u003c\/p\u003e \u003cp\u003e10.10.4 System time display 256\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 FPro Bus Protocol and MMIO Slot Specification 257\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 FPro bus 257\u003c\/p\u003e \u003cp\u003e11.1.1 Overview of the bus 257\u003c\/p\u003e \u003cp\u003e11.1.2 SoC interconnect 258\u003c\/p\u003e \u003cp\u003e11.1.3 FPro bus protocol specification 259\u003c\/p\u003e \u003cp\u003e11.2 Interface with the bus 260\u003c\/p\u003e \u003cp\u003e11.2.1 Introduction 260\u003c\/p\u003e \u003cp\u003e11.2.2 Write interface and decoding 261\u003c\/p\u003e \u003cp\u003e11.2.3 Read interface and multiplexing 263\u003c\/p\u003e \u003cp\u003e11.2.4 FIFO buffer as an I\/O register 264\u003c\/p\u003e \u003cp\u003e11.2.5 Timing consideration 265\u003c\/p\u003e \u003cp\u003e11.3 MMIO I\/O core 266\u003c\/p\u003e \u003cp\u003e11.3.1 MMIO slot interface specification 266\u003c\/p\u003e \u003cp\u003e11.3.2 Basic MMIO I\/O core construction 268\u003c\/p\u003e \u003cp\u003e11.3.3 GPO and GPI cores 269\u003c\/p\u003e \u003cp\u003e11.4 Timer core development 270\u003c\/p\u003e \u003cp\u003e11.4.1 Custom logic 270\u003c\/p\u003e \u003cp\u003e11.4.2 Register map 271\u003c\/p\u003e \u003cp\u003e11.4.3 Wrapping circuit for the slot interface 271\u003c\/p\u003e \u003cp\u003e11.5 MMIO controller 272\u003c\/p\u003e \u003cp\u003e11.5.1 chu_io_map.svh file 273\u003c\/p\u003e \u003cp\u003e11.5.2 HDL code 273\u003c\/p\u003e \u003cp\u003e11.5.3 Vanilla MMIO subsystem 275\u003c\/p\u003e \u003cp\u003e11.6 MCS I\/O bus and bridge 278\u003c\/p\u003e \u003cp\u003e11.6.1 Overview of Xilinx MicroBlaze MCS 278\u003c\/p\u003e \u003cp\u003e11.6.2 MicroBlaze MCS I\/O bus 278\u003c\/p\u003e \u003cp\u003e11.6.3 MCS-to-FPro bridge 279\u003c\/p\u003e \u003cp\u003e11.7 Vanilla FPro system construction 281\u003c\/p\u003e \u003cp\u003e11.8 Bibliographic notes 282\u003c\/p\u003e \u003cp\u003e11.9 Suggested experiments 283\u003c\/p\u003e \u003cp\u003e11.9.1 FPro bus with a byte-lane enable signal 283\u003c\/p\u003e \u003cp\u003e11.9.2 Seven-segment control with a GPO core 283\u003c\/p\u003e \u003cp\u003e11.9.3 GPIO core 283\u003c\/p\u003e \u003cp\u003e11.9.4 Blinking-LED core 284\u003c\/p\u003e \u003cp\u003e11.9.5 Timer core with a programmable period 284\u003c\/p\u003e \u003cp\u003e11.9.6 Timer core with a run-once mode 284\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 UART Core 287\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction 287\u003c\/p\u003e \u003cp\u003e12.1.1 Overview of serial communication 287\u003c\/p\u003e \u003cp\u003e12.1.2 Overview of the UART 288\u003c\/p\u003e \u003cp\u003e12.1.3 Oversampling procedure 288\u003c\/p\u003e \u003cp\u003e12.2 UART construction 289\u003c\/p\u003e \u003cp\u003e12.2.1 Conceptual design 289\u003c\/p\u003e \u003cp\u003e12.2.2 Baud rate generator 290\u003c\/p\u003e \u003cp\u003e12.2.3 UART receiver 291\u003c\/p\u003e \u003cp\u003e12.2.4 UART transmitter 293\u003c\/p\u003e \u003cp\u003e12.2.5 Top-level HDL code 295\u003c\/p\u003e \u003cp\u003e12.3 UART core development 296\u003c\/p\u003e \u003cp\u003e12.3.1 Register map 296\u003c\/p\u003e \u003cp\u003e12.3.2 Wrapping circuit for the slot interface 297\u003c\/p\u003e \u003cp\u003e12.4 UART driver 298\u003c\/p\u003e \u003cp\u003e12.4.1 Class definition 299\u003c\/p\u003e \u003cp\u003e12.4.2 Basic methods 300\u003c\/p\u003e \u003cp\u003e12.4.3 ASCII code 301\u003c\/p\u003e \u003cp\u003e12.4.4 Display methods 303\u003c\/p\u003e \u003cp\u003e12.4.5 Test 305\u003c\/p\u003e \u003cp\u003e12.5 Additional project ideas 305\u003c\/p\u003e \u003cp\u003e12.5.1 Original serial port 305\u003c\/p\u003e \u003cp\u003e12.5.2 Emulated serial port 305\u003c\/p\u003e \u003cp\u003e12.5.3 Direct connection 306\u003c\/p\u003e \u003cp\u003e12.5.4 USB-to-UART adaptor 306\u003c\/p\u003e \u003cp\u003e12.5.5 Wireless adaptor 307\u003c\/p\u003e \u003cp\u003e12.6 Bibliographic notes 308\u003c\/p\u003e \u003cp\u003e12.7 Suggested experiments 308\u003c\/p\u003e \u003cp\u003e12.7.1 UART-controlled chasing LEDs 308\u003c\/p\u003e \u003cp\u003e12.7.2 Alternative read configuration 308\u003c\/p\u003e \u003cp\u003e12.7.3 UART controller with a parity bit 308\u003c\/p\u003e \u003cp\u003e12.7.4 UART core with an error status 309\u003c\/p\u003e \u003cp\u003e12.7.5 Configurable UART core 309\u003c\/p\u003e \u003cp\u003e12.7.6 UART core with automatic baud rate detection 309\u003c\/p\u003e \u003cp\u003e12.7.7 UART core with enhanced automatic baud rate detection 310\u003c\/p\u003e \u003cp\u003e12.7.8 UART core with an automatic baud rate and a parity detection circuit 310\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART III EMBEDDED SOC II: BASIC I\/O CORES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Xilinx XADC Core 313\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Overview of XADC 313\u003c\/p\u003e \u003cp\u003e13.1.1 Block diagram 313\u003c\/p\u003e \u003cp\u003e13.1.2 Configuration 314\u003c\/p\u003e \u003cp\u003e13.2 XADC core development 315\u003c\/p\u003e \u003cp\u003e13.2.1 XADC instantiation 315\u003c\/p\u003e \u003cp\u003e13.2.2 Basic wrapping circuit design 316\u003c\/p\u003e \u003cp\u003e13.2.3 Register map 318\u003c\/p\u003e \u003cp\u003e13.2.4 HDL code 318\u003c\/p\u003e \u003cp\u003e13.3 XADC core device driver 320\u003c\/p\u003e \u003cp\u003e13.3.1 Class definition 320\u003c\/p\u003e \u003cp\u003e13.3.2 Class implementation 321\u003c\/p\u003e \u003cp\u003e13.3.3 Testing for the XADC core 322\u003c\/p\u003e \u003cp\u003e13.4 Sampler FPro system 323\u003c\/p\u003e \u003cp\u003e13.4.1 Testing procedure of an FPro core 323\u003c\/p\u003e \u003cp\u003e13.4.2 System configuration 323\u003c\/p\u003e \u003cp\u003e13.4.3 Hardware derivation 324\u003c\/p\u003e \u003cp\u003e13.4.4 Software verification program 331\u003c\/p\u003e \u003cp\u003e13.5 Additional project ideas 332\u003c\/p\u003e \u003cp\u003e13.6 Bibliographic notes 333\u003c\/p\u003e \u003cp\u003e13.7 Suggested experiments 333\u003c\/p\u003e \u003cp\u003e13.7.1 Real-time voltage display 333\u003c\/p\u003e \u003cp\u003e13.7.2 Potentiometer-controlled chasing LEDs 333\u003c\/p\u003e \u003cp\u003e13.7.3 Potentiometer-controlled LED dimmer 333\u003c\/p\u003e \u003cp\u003e13.7.4 Enhanced wrapping circuit: part I 333\u003c\/p\u003e \u003cp\u003e13.7.5 Enhanced wrapping circuit: part II 333\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Pulse Width Modulation Core 335\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction 335\u003c\/p\u003e \u003cp\u003e14.1.1 PWM as analog output 335\u003c\/p\u003e \u003cp\u003e14.1.2 Main characteristics 336\u003c\/p\u003e \u003cp\u003e14.2 PWM design 336\u003c\/p\u003e \u003cp\u003e14.2.1 Basic design 336\u003c\/p\u003e \u003cp\u003e14.2.2 Enhanced design 337\u003c\/p\u003e \u003cp\u003e14.3 PWM core development 339\u003c\/p\u003e \u003cp\u003e14.3.1 Register map 339\u003c\/p\u003e \u003cp\u003e14.3.2 Wrapped PWM circuit 340\u003c\/p\u003e \u003cp\u003e14.4 PWM driver 341\u003c\/p\u003e \u003cp\u003e14.4.1 Class definition 341\u003c\/p\u003e \u003cp\u003e14.4.2 Class implementation 342\u003c\/p\u003e \u003cp\u003e14.5 Testing 343\u003c\/p\u003e \u003cp\u003e14.6 Project ideas 343\u003c\/p\u003e \u003cp\u003e14.7 Suggested experiments 345\u003c\/p\u003e \u003cp\u003e14.7.1 Police dash light 345\u003c\/p\u003e \u003cp\u003e14.7.2 Rainbow night light 345\u003c\/p\u003e \u003cp\u003e14.7.3 Enhanced PWM core: part I 345\u003c\/p\u003e \u003cp\u003e14.7.4 Enhanced PWM core: part II 346\u003c\/p\u003e \u003cp\u003e14.7.5 Enhanced GPIO core 346\u003c\/p\u003e \u003cp\u003e14.7.6 Servo motor driver 346\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Debouncing Core and LED-Mux Core 347\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Debouncing Core 347\u003c\/p\u003e \u003cp\u003e15.1.1 Multi-bit debouncing circuit 347\u003c\/p\u003e \u003cp\u003e15.1.2 Register map and the slot wrapping circuit 350\u003c\/p\u003e \u003cp\u003e15.1.3 Driver 351\u003c\/p\u003e \u003cp\u003e15.1.4 Test 352\u003c\/p\u003e \u003cp\u003e15.2 LED-mux core 352\u003c\/p\u003e \u003cp\u003e15.2.1 Eight-digit seven-segment LED display multiplexing circuit 352\u003c\/p\u003e \u003cp\u003e15.2.2 Register map and the slot wrapping circuit 354\u003c\/p\u003e \u003cp\u003e15.2.3 Driver 355\u003c\/p\u003e \u003cp\u003e15.2.4 Test 358\u003c\/p\u003e \u003cp\u003e15.3 Project ideas 358\u003c\/p\u003e \u003cp\u003e15.4 Suggested experiments 360\u003c\/p\u003e \u003cp\u003e15.4.1 Area comparison of two debouncing circuits 360\u003c\/p\u003e \u003cp\u003e15.4.2 Enhanced debouncing core: part I 360\u003c\/p\u003e \u003cp\u003e15.4.3 Enhanced debouncing core: part II 360\u003c\/p\u003e \u003cp\u003e15.4.4 Rotating square pattern revisited 360\u003c\/p\u003e \u003cp\u003e15.4.5 Heartbeat pattern revisited 360\u003c\/p\u003e \u003cp\u003e15.4.6 Stopwatch 360\u003c\/p\u003e \u003cp\u003e15.4.7 Enhanced LED-mux core 361\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 SPI Core 363\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Overview 363\u003c\/p\u003e \u003cp\u003e16.1.1 Conceptual architecture 364\u003c\/p\u003e \u003cp\u003e16.1.2 Multiple-device configuration 364\u003c\/p\u003e \u003cp\u003e16.1.3 Basic timing 366\u003c\/p\u003e \u003cp\u003e16.1.4 Operation modes 367\u003c\/p\u003e \u003cp\u003e16.1.5 Undefined aspects 368\u003c\/p\u003e \u003cp\u003e16.2 SPI controller 369\u003c\/p\u003e \u003cp\u003e16.2.1 Basic design 369\u003c\/p\u003e \u003cp\u003e16.2.2 FSMD construction 370\u003c\/p\u003e \u003cp\u003e16.2.3 HDL implementation 370\u003c\/p\u003e \u003cp\u003e16.3 SPI core development 374\u003c\/p\u003e \u003cp\u003e16.3.1 Register map 374\u003c\/p\u003e \u003cp\u003e16.3.2 Wrapping circuit for the slot interface 374\u003c\/p\u003e \u003cp\u003e16.4 SPI driver 376\u003c\/p\u003e \u003cp\u003e16.4.1 Class definition 376\u003c\/p\u003e \u003cp\u003e16.4.2 Class implementation 377\u003c\/p\u003e \u003cp\u003e16.5 Test 378\u003c\/p\u003e \u003cp\u003e16.5.1 ADXL362 accelerometer 378\u003c\/p\u003e \u003cp\u003e16.5.2 Test program 380\u003c\/p\u003e \u003cp\u003e16.6 Project ideas 381\u003c\/p\u003e \u003cp\u003e16.6.1 SD card 381\u003c\/p\u003e \u003cp\u003e16.6.2 TFT LCD module 382\u003c\/p\u003e \u003cp\u003e16.7 Bibliographic notes 382\u003c\/p\u003e \u003cp\u003e16.8 Suggested experiments 382\u003c\/p\u003e \u003cp\u003e16.8.1 Inclination sensing 382\u003c\/p\u003e \u003cp\u003e16.8.2 “Tapping” detection 382\u003c\/p\u003e \u003cp\u003e16.8.3 ADXL362 C++ class 383\u003c\/p\u003e \u003cp\u003e16.8.4 Enhanced SPI controller: part I 383\u003c\/p\u003e \u003cp\u003e16.8.5 Enhanced SPI controller: part II 383\u003c\/p\u003e \u003cp\u003e16.8.6 “Automatic-read” ADXL362 wrapper: part I 383\u003c\/p\u003e \u003cp\u003e16.8.7 “Automatic-read” ADXL362 wrapper: part II 384\u003c\/p\u003e \u003cp\u003e16.8.8 Flash memory access 384\u003c\/p\u003e \u003cp\u003e16.8.9 SPI slave controller: part I 384\u003c\/p\u003e \u003cp\u003e16.8.10 SPI slave controller: part II 385\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 \u003c\/b\u003eI\u003csup\u003e2\u003c\/sup\u003eC\u003cb\u003e Core 387\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Overview 387\u003c\/p\u003e \u003cp\u003e17.1.1 Electrical characteristics 388\u003c\/p\u003e \u003cp\u003e17.1.2 Basic bus protocol 388\u003c\/p\u003e \u003cp\u003e17.1.3 Basic timing 389\u003c\/p\u003e \u003cp\u003e17.1.4 Additional features 390\u003c\/p\u003e \u003cp\u003e17.2 I\u003csup\u003e2\u003c\/sup\u003eC controller 391\u003c\/p\u003e \u003cp\u003e17.2.1 Basic design 391\u003c\/p\u003e \u003cp\u003e17.2.2 Conceptual FSMD construction 391\u003c\/p\u003e \u003cp\u003e17.2.3 Output control logic 394\u003c\/p\u003e \u003cp\u003e17.2.4 I\u003csup\u003e2\u003c\/sup\u003eC bus clock generation 394\u003c\/p\u003e \u003cp\u003e17.2.5 HDL implementation 395\u003c\/p\u003e \u003cp\u003e17.3 I\u003csup\u003e2\u003c\/sup\u003eC core development 400\u003c\/p\u003e \u003cp\u003e17.3.1 Register map 400\u003c\/p\u003e \u003cp\u003e17.3.2 Wrapping circuit for the slot interface 400\u003c\/p\u003e \u003cp\u003e17.4 I\u003csup\u003e2\u003c\/sup\u003eC driver 401\u003c\/p\u003e \u003cp\u003e17.4.1 Class definition 401\u003c\/p\u003e \u003cp\u003e17.4.2 Class implementation 402\u003c\/p\u003e \u003cp\u003e17.5 Test 405\u003c\/p\u003e \u003cp\u003e17.5.1 ADT7420 temperature sensor 405\u003c\/p\u003e \u003cp\u003e17.5.2 Test program 406\u003c\/p\u003e \u003cp\u003e17.6 Project idea 406\u003c\/p\u003e \u003cp\u003e17.7 Bibliographic notes 407\u003c\/p\u003e \u003cp\u003e17.8 Suggested experiments 407\u003c\/p\u003e \u003cp\u003e17.8.1 Thermometer 407\u003c\/p\u003e \u003cp\u003e17.8.2 ADT7420 C++ class 407\u003c\/p\u003e \u003cp\u003e17.8.3 Enhanced I\u003csup\u003e2\u003c\/sup\u003eC core 408\u003c\/p\u003e \u003cp\u003e17.8.4 “Automatic-read” ADT7420 wrapper 408\u003c\/p\u003e \u003cp\u003e17.8.5 I\u003csup\u003e2\u003c\/sup\u003eC slave controller: part I 408\u003c\/p\u003e \u003cp\u003e17.8.6 I\u003csup\u003e2\u003c\/sup\u003eC slave controller: part II 408\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 PS2 Core 409\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Introduction 409\u003c\/p\u003e \u003cp\u003e18.1.1 PS2-device-to-host communication protocol and timing 410\u003c\/p\u003e \u003cp\u003e18.1.2 Host-to-PS2-device communication protocol and timing 410\u003c\/p\u003e \u003cp\u003e18.2 PS2 controller 411\u003c\/p\u003e \u003cp\u003e18.2.1 Conceptual design 411\u003c\/p\u003e \u003cp\u003e18.2.2 PS2 receiving subsystem 411\u003c\/p\u003e \u003cp\u003e18.2.3 PS2 transmitting subsystem 415\u003c\/p\u003e \u003cp\u003e18.2.4 Complete PS2 system 419\u003c\/p\u003e \u003cp\u003e18.3 PS2 core development 420\u003c\/p\u003e \u003cp\u003e18.3.1 Register map 420\u003c\/p\u003e \u003cp\u003e18.3.2 Wrapping circuit for the slot interface 421\u003c\/p\u003e \u003cp\u003e18.4 PS2 driver 422\u003c\/p\u003e \u003cp\u003e18.4.1 Class definition 422\u003c\/p\u003e \u003cp\u003e18.4.2 Lower layer methods 422\u003c\/p\u003e \u003cp\u003e18.4.3 PS2 initialization routine 423\u003c\/p\u003e \u003cp\u003e18.4.4 Keyboard routine 425\u003c\/p\u003e \u003cp\u003e18.4.5 Mouse routine 428\u003c\/p\u003e \u003cp\u003e18.5 Test 430\u003c\/p\u003e \u003cp\u003e18.6 Bibliographic notes 431\u003c\/p\u003e \u003cp\u003e18.7 Suggested experiments 431\u003c\/p\u003e \u003cp\u003e18.7.1 PS2 receiving subsystem with watchdog timer 431\u003c\/p\u003e \u003cp\u003e18.7.2 Keyboard-controlled LED flashing circuit 432\u003c\/p\u003e \u003cp\u003e18.7.3 Enhanced keyboard driver routine: part I 432\u003c\/p\u003e \u003cp\u003e18.7.4 Enhanced keyboard driver routine: part II 432\u003c\/p\u003e \u003cp\u003e18.7.5 Remote-mode mouse driver 432\u003c\/p\u003e \u003cp\u003e18.7.6 Scroll-wheel mouse driver 432\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 Sound I: DDFS Core 433\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Introduction 433\u003c\/p\u003e \u003cp\u003e19.2 Design and implementation 434\u003c\/p\u003e \u003cp\u003e19.2.1 Direct synthesis of a digital waveform 434\u003c\/p\u003e \u003cp\u003e19.2.2 Direct synthesis of an unmodulated analog waveform 435\u003c\/p\u003e \u003cp\u003e19.2.3 Direct synthesis of a modulated analog waveform 436\u003c\/p\u003e \u003cp\u003e19.3 Fixed-point arithmetic 437\u003c\/p\u003e \u003cp\u003e19.4 DDFS construction 438\u003c\/p\u003e \u003cp\u003e19.5 DAC (digital-to-analog converter) 440\u003c\/p\u003e \u003cp\u003e19.5.1 Conceptual design 440\u003c\/p\u003e \u003cp\u003e19.5.2 HDL implementation 441\u003c\/p\u003e \u003cp\u003e19.6 DDFS core development 442\u003c\/p\u003e \u003cp\u003e19.6.1 Register map 442\u003c\/p\u003e \u003cp\u003e19.6.2 Wrapping circuit for the slot interface 443\u003c\/p\u003e \u003cp\u003e19.7 DDFS driver 444\u003c\/p\u003e \u003cp\u003e19.7.1 Class definition 444\u003c\/p\u003e \u003cp\u003e19.7.2 Class implementation 445\u003c\/p\u003e \u003cp\u003e19.8 Test 447\u003c\/p\u003e \u003cp\u003e19.9 Bibliographic notes 448\u003c\/p\u003e \u003cp\u003e19.10 Suggested experiments 448\u003c\/p\u003e \u003cp\u003e19.10.1 Quadrature phase carrier generation 448\u003c\/p\u003e \u003cp\u003e19.10.2 Reduced-size phase-to-amplitude lookup table 448\u003c\/p\u003e \u003cp\u003e19.10.3 Additive harmonic synthesis 449\u003c\/p\u003e \u003cp\u003e19.10.4 Simple function generator 449\u003c\/p\u003e \u003cp\u003e19.10.5 Arbitrary waveform generator 449\u003c\/p\u003e \u003cp\u003e19.10.6 Sample-based synthesis 449\u003c\/p\u003e \u003cp\u003e\u003cb\u003e20 Sound II: ADSR Core 451\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e20.1 Introduction 451\u003c\/p\u003e \u003cp\u003e20.2 ADSR envelope generator 452\u003c\/p\u003e \u003cp\u003e20.2.1 Conceptual FSMD design 453\u003c\/p\u003e \u003cp\u003e20.2.2 ASMD chart 453\u003c\/p\u003e \u003cp\u003e20.2.3 HDL implementation 455\u003c\/p\u003e \u003cp\u003e20.3 ADSR core development 457\u003c\/p\u003e \u003cp\u003e20.3.1 Register map 457\u003c\/p\u003e \u003cp\u003e20.3.2 Wrapped ADSR circuit 458\u003c\/p\u003e \u003cp\u003e20.4 ADSR driver 460\u003c\/p\u003e \u003cp\u003e20.4.1 Class definition 460\u003c\/p\u003e \u003cp\u003e20.4.2 Configuration methods 461\u003c\/p\u003e \u003cp\u003e20.4.3 calc note freq() method 463\u003c\/p\u003e \u003cp\u003e20.4.4 play note() method 465\u003c\/p\u003e \u003cp\u003e20.5 Test 465\u003c\/p\u003e \u003cp\u003e20.6 Project idea 466\u003c\/p\u003e \u003cp\u003e20.7 Bibliographic notes 467\u003c\/p\u003e \u003cp\u003e20.8 Suggested experiments 467\u003c\/p\u003e \u003cp\u003e20.8.1 RTTTL music player 467\u003c\/p\u003e \u003cp\u003e20.8.2 ADSR envelope testing 467\u003c\/p\u003e \u003cp\u003e20.8.3 Pushbutton piano 467\u003c\/p\u003e \u003cp\u003e20.8.4 Keyboard piano 468\u003c\/p\u003e \u003cp\u003e20.8.5 Keyboard recorder 468\u003c\/p\u003e \u003cp\u003e20.8.6 Real-time mode ADSR generator 468\u003c\/p\u003e \u003cp\u003e20.8.7 Real-time mode pushbutton piano 468\u003c\/p\u003e \u003cp\u003e20.8.8 Merged DDFS and ADSR core 468\u003c\/p\u003e \u003cp\u003e20.8.9 ADSR core with an automatic play FIFO buffer 468\u003c\/p\u003e \u003cp\u003e20.8.10 ADSR core for frequency modulation 468\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART IV EMBEDDED SOC III: VIDEO CORES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e21 Introduction to the Video System 471\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e21.1 Introduction to a video display 471\u003c\/p\u003e \u003cp\u003e21.1.1 Conceptual video display 471\u003c\/p\u003e \u003cp\u003e21.1.2 VGA interface 472\u003c\/p\u003e \u003cp\u003e21.2 Stream interface 473\u003c\/p\u003e \u003cp\u003e21.2.1 Random-access interface versus stream interface 473\u003c\/p\u003e \u003cp\u003e21.2.2 Flow control of the stream interface 473\u003c\/p\u003e \u003cp\u003e21.3 VGA synchronization 475\u003c\/p\u003e \u003cp\u003e21.3.1 Basic operation of a CRT monitor 475\u003c\/p\u003e \u003cp\u003e21.3.2 Horizontal synchronization 476\u003c\/p\u003e \u003cp\u003e21.3.3 Vertical synchronization 478\u003c\/p\u003e \u003cp\u003e21.3.4 Pixel clock rate 479\u003c\/p\u003e \u003cp\u003e21.3.5 VGA synchronization circuit 480\u003c\/p\u003e \u003cp\u003e21.4 Bar test-pattern generator 483\u003c\/p\u003e \u003cp\u003e21.5 Color-to-grayscale conversion circuit 485\u003c\/p\u003e \u003cp\u003e21.6 Demo video system 486\u003c\/p\u003e \u003cp\u003e21.7 Advanced video standards 488\u003c\/p\u003e \u003cp\u003e21.8 Bibliographic notes 489\u003c\/p\u003e \u003cp\u003e21.9 Suggested experiments 489\u003c\/p\u003e \u003cp\u003e21.9.1 Horizontal bar test-pattern generator 489\u003c\/p\u003e \u003cp\u003e21.9.2 Color channel selection circuit 489\u003c\/p\u003e \u003cp\u003e21.9.3 Enhanced color-to-grayscale conversion circuit 489\u003c\/p\u003e \u003cp\u003e21.9.4 Square test-pattern generator: part I 489\u003c\/p\u003e \u003cp\u003e21.9.5 Square test-pattern generator: part II 489\u003c\/p\u003e \u003cp\u003e21.9.6 Square test-pattern generator: part III 490\u003c\/p\u003e \u003cp\u003e21.9.7 Square test-pattern generator: part IV 490\u003c\/p\u003e \u003cp\u003e\u003cb\u003e22 FPro Video Subsystem 491\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e22.1 Organization of the video subsystem 491\u003c\/p\u003e \u003cp\u003e22.1.1 Overview 491\u003c\/p\u003e \u003cp\u003e22.1.2 Video controller 493\u003c\/p\u003e \u003cp\u003e22.1.3 HDL of the video controller 494\u003c\/p\u003e \u003cp\u003e22.2 FPro video IP core 495\u003c\/p\u003e \u003cp\u003e22.2.1 Basic functionality 495\u003c\/p\u003e \u003cp\u003e22.2.2 Blending operation 496\u003c\/p\u003e \u003cp\u003e22.2.3 Core architecture 498\u003c\/p\u003e \u003cp\u003e22.2.4 Alternative core partition 500\u003c\/p\u003e \u003cp\u003e22.3 Example video cores 500\u003c\/p\u003e \u003cp\u003e22.3.1 Bar test-pattern generator core 500\u003c\/p\u003e \u003cp\u003e22.3.2 Color-to-grayscale conversion core 503\u003c\/p\u003e \u003cp\u003e22.3.3 “Dummy” core 504\u003c\/p\u003e \u003cp\u003e22.4 FPro video synchronization core 504\u003c\/p\u003e \u003cp\u003e22.4.1 Line buffer 505\u003c\/p\u003e \u003cp\u003e22.4.2 Enhanced video synchronization circuit 508\u003c\/p\u003e \u003cp\u003e22.4.3 HDL code 511\u003c\/p\u003e \u003cp\u003e22.5 Daisy video subsystem 512\u003c\/p\u003e \u003cp\u003e22.5.1 Subsystem overview 512\u003c\/p\u003e \u003cp\u003e22.5.2 Interface to the video synchronization core 513\u003c\/p\u003e \u003cp\u003e22.5.3 HDL code 513\u003c\/p\u003e \u003cp\u003e22.5.4 Timing and performance considerations 517\u003c\/p\u003e \u003cp\u003e22.6 Vanilla daisy FPro system 517\u003c\/p\u003e \u003cp\u003e22.6.1 Clock management core 518\u003c\/p\u003e \u003cp\u003e22.6.2 Updated chu_io_map.svh 519\u003c\/p\u003e \u003cp\u003e22.6.3 HDL code 519\u003c\/p\u003e \u003cp\u003e22.7 Video driver and test program 521\u003c\/p\u003e \u003cp\u003e22.7.1 Updated chu_io_map.h and chu_io_rw.h files 521\u003c\/p\u003e \u003cp\u003e22.7.2 GPV core driver 522\u003c\/p\u003e \u003cp\u003e22.7.3 Test program 523\u003c\/p\u003e \u003cp\u003e22.8 Bibliographic notes 524\u003c\/p\u003e \u003cp\u003e22.9 Suggested experiments 525\u003c\/p\u003e \u003cp\u003e22.9.1 Color channel selection core 525\u003c\/p\u003e \u003cp\u003e22.9.2 Enhanced color-to-grayscale conversion core 525\u003c\/p\u003e \u003cp\u003e22.9.3 Square test-pattern generator core 525\u003c\/p\u003e \u003cp\u003e22.9.4 Alpha blending circuit 525\u003c\/p\u003e \u003cp\u003e22.9.5 “Highlight” core 525\u003c\/p\u003e \u003cp\u003e22.9.6 SVGA synchronization core 526\u003c\/p\u003e \u003cp\u003e22.9.7 Configurable video synchronization core 526\u003c\/p\u003e \u003cp\u003e22.9.8 Pipelined video subsystem 526\u003c\/p\u003e \u003cp\u003e\u003cb\u003e23 Sprite Core 527\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e23.1 Introduction 527\u003c\/p\u003e \u003cp\u003e23.2 Basic design 528\u003c\/p\u003e \u003cp\u003e23.2.1 Sprite RAM 528\u003c\/p\u003e \u003cp\u003e23.2.2 In-region comparison circuit 529\u003c\/p\u003e \u003cp\u003e23.3 Mouse pointer core 530\u003c\/p\u003e \u003cp\u003e23.3.1 Pointer sprite RAM 530\u003c\/p\u003e \u003cp\u003e23.3.2 Pixel generation circuit 531\u003c\/p\u003e \u003cp\u003e23.3.3 Top-level design 532\u003c\/p\u003e \u003cp\u003e23.4 “Ghost” character core 534\u003c\/p\u003e \u003cp\u003e23.4.1 Multiple images and animation 534\u003c\/p\u003e \u003cp\u003e23.4.2 Overview of the palette scheme 535\u003c\/p\u003e \u003cp\u003e23.4.3 Ghost sprite RAM and the palette circuit 535\u003c\/p\u003e \u003cp\u003e23.4.4 Animation timing circuit 537\u003c\/p\u003e \u003cp\u003e23.4.5 Pixel generation circuit 537\u003c\/p\u003e \u003cp\u003e23.4.6 Top-level design 540\u003c\/p\u003e \u003cp\u003e23.5 Sprite core driver and test program 541\u003c\/p\u003e \u003cp\u003e23.5.1 Sprite core driver 541\u003c\/p\u003e \u003cp\u003e23.5.2 Test program 543\u003c\/p\u003e \u003cp\u003e23.6 Bibliographic notes 544\u003c\/p\u003e \u003cp\u003e23.7 Suggested experiments 544\u003c\/p\u003e \u003cp\u003e23.7.1 Mouse pointer control with PS2 core 544\u003c\/p\u003e \u003cp\u003e23.7.2 Emulated ghost core 544\u003c\/p\u003e \u003cp\u003e23.7.3 Palette circuit for the mouse pointer sprite 544\u003c\/p\u003e \u003cp\u003e23.7.4 Sprite scaling circuit 544\u003c\/p\u003e \u003cp\u003e23.7.5 Portrait mode display 545\u003c\/p\u003e \u003cp\u003e23.7.6 Multiple-object generation 545\u003c\/p\u003e \u003cp\u003e23.7.7 Animation speed control 545\u003c\/p\u003e \u003cp\u003e23.7.8 Imitated blinking LED: part I 545\u003c\/p\u003e \u003cp\u003e23.7.9 Imitated blinking LED: part II 545\u003c\/p\u003e \u003cp\u003e23.7.10 Imitated blinking LED: part III 546\u003c\/p\u003e \u003cp\u003e\u003cb\u003e24 On-Screen-Display Core 547\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e24.1 Introduction to tile graphics 547\u003c\/p\u003e \u003cp\u003e24.2 Basic OSD design 549\u003c\/p\u003e \u003cp\u003e24.2.1 Text-mode display 549\u003c\/p\u003e \u003cp\u003e24.2.2 Font ROM 550\u003c\/p\u003e \u003cp\u003e24.2.3 Tile RAM 550\u003c\/p\u003e \u003cp\u003e24.2.4 Basic organization 551\u003c\/p\u003e \u003cp\u003e24.3 OSD core 552\u003c\/p\u003e \u003cp\u003e24.3.1 Font ROM 552\u003c\/p\u003e \u003cp\u003e24.3.2 Pixel generation circuit 553\u003c\/p\u003e \u003cp\u003e24.3.3 Top-level design 555\u003c\/p\u003e \u003cp\u003e24.4 OSD core driver and test program 557\u003c\/p\u003e \u003cp\u003e24.4.1 OSD core driver 557\u003c\/p\u003e \u003cp\u003e24.4.2 Testing program 558\u003c\/p\u003e \u003cp\u003e24.5 Bibliographic notes 559\u003c\/p\u003e \u003cp\u003e24.6 Suggested experiments 559\u003c\/p\u003e \u003cp\u003e24.6.1 Rotating banner 559\u003c\/p\u003e \u003cp\u003e24.6.2 Text console 559\u003c\/p\u003e \u003cp\u003e24.6.3 Underline for the cursor 559\u003c\/p\u003e \u003cp\u003e24.6.4 Portrait-mode display 560\u003c\/p\u003e \u003cp\u003e24.6.5 Font scaling circuit: part I 560\u003c\/p\u003e \u003cp\u003e24.6.6 Font scaling circuit: part II 560\u003c\/p\u003e \u003cp\u003e24.6.7 Extended font 560\u003c\/p\u003e \u003cp\u003e24.6.8 Tile-based ghost core 560\u003c\/p\u003e \u003cp\u003e\u003cb\u003e25 VGA Frame Buffer Core 561\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e25.1 Overview 561\u003c\/p\u003e \u003cp\u003e25.2 Frame buffer core 562\u003c\/p\u003e \u003cp\u003e25.2.1 FPGA memory consideration 562\u003c\/p\u003e \u003cp\u003e25.2.2 Video memory module 562\u003c\/p\u003e \u003cp\u003e25.2.3 Address translation 563\u003c\/p\u003e \u003cp\u003e25.2.4 Pixel generation circuit 564\u003c\/p\u003e \u003cp\u003e25.2.5 Register map 566\u003c\/p\u003e \u003cp\u003e25.2.6 Top-level HDL code 566\u003c\/p\u003e \u003cp\u003e25.3 Driver and test program 567\u003c\/p\u003e \u003cp\u003e25.3.1 Frame buffer core driver 567\u003c\/p\u003e \u003cp\u003e25.3.2 Geometrical modeling 568\u003c\/p\u003e \u003cp\u003e25.3.3 Test program 570\u003c\/p\u003e \u003cp\u003e25.4 Project ideas 570\u003c\/p\u003e \u003cp\u003e25.5 Bibliographic notes 572\u003c\/p\u003e \u003cp\u003e25.6 Suggested experiments 572\u003c\/p\u003e \u003cp\u003e25.6.1 Virtual prototyping board panel 572\u003c\/p\u003e \u003cp\u003e25.6.2 Virtual analog wall clock 572\u003c\/p\u003e \u003cp\u003e25.6.3 Geometrical model functions 572\u003c\/p\u003e \u003cp\u003e25.6.4 Simulated “Etch a Sketch” toy 572\u003c\/p\u003e \u003cp\u003e25.6.5 Frame buffer core with 3-bit color depth 573\u003c\/p\u003e \u003cp\u003e25.6.6 Frame buffer core with 1-bit color depth 573\u003c\/p\u003e \u003cp\u003e25.6.7 QVGA frame buffer core 573\u003c\/p\u003e \u003cp\u003e25.6.8 Line drawing hardware accelerator 573\u003c\/p\u003e \u003cp\u003e25.6.9 Bidirectional frame buffer access: part I 573\u003c\/p\u003e \u003cp\u003e25.6.10 Bidirectional frame buffer access: part II 573\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART V EPILOGUE\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e26 What’s Next 577\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 581\u003c\/p\u003e \u003cp\u003eAppendix A: Tutorials 585\u003c\/p\u003e \u003cp\u003eA.1 Overview of Xilinx Vivado IDE 585\u003c\/p\u003e \u003cp\u003eA.2 Short tutorial on Vivado hardware development 589\u003c\/p\u003e \u003cp\u003eA.2.1 Create a design project 590\u003c\/p\u003e \u003cp\u003eA.2.2 Add or create Xilinx IP core instances 591\u003c\/p\u003e \u003cp\u003eA.2.3 Add or create HDL design files 591\u003c\/p\u003e \u003cp\u003eA.2.4 Add a constraint file 592\u003c\/p\u003e \u003cp\u003eA.2.5 Perform synthesis, implementation, and bitstream generation 593\u003c\/p\u003e \u003cp\u003eA.2.6 Program an FPGA device 593\u003c\/p\u003e \u003cp\u003eA.3 Short tutorial on Vivado simulation 594\u003c\/p\u003e \u003cp\u003eA.3.1 Add or create HDL testbench 596\u003c\/p\u003e \u003cp\u003eA.3.2 Perform initial simulation 596\u003c\/p\u003e \u003cp\u003eA.3.3 Customize waveform display 597\u003c\/p\u003e \u003cp\u003eA.4 Tutorial on IP instantiation 597\u003c\/p\u003e \u003cp\u003eA.4.1 Dual-clock FIFO core via HDL templates 598\u003c\/p\u003e \u003cp\u003eA.4.2 IP Catalog utility 599\u003c\/p\u003e \u003cp\u003eA.4.3 Generate a MicroBlaze MCS component 600\u003c\/p\u003e \u003cp\u003eA.4.4 XADC IP core 601\u003c\/p\u003e \u003cp\u003eA.4.5 Clock management IP core 602\u003c\/p\u003e \u003cp\u003eA.5 Short tutorial on FPro system development 604\u003c\/p\u003e \u003cp\u003eA.5.1 Derive FPro system hardware 605\u003c\/p\u003e \u003cp\u003eA.5.2 Export hardware configuration 605\u003c\/p\u003e \u003cp\u003eA.5.3 Derive software 605\u003c\/p\u003e \u003cp\u003eA.5.4 Embed elf file into FPGA’s memory module and regenerate bitstream 608\u003c\/p\u003e \u003cp\u003eA.5.5 Set up the terminal emulator program 610\u003c\/p\u003e \u003cp\u003eA.5.6 Program an FPGA device 610\u003c\/p\u003e \u003cp\u003eA.6 Bibliographic notes 611\u003c\/p\u003e \u003cp\u003eTopic Index 613\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley","offers":[{"title":"Brand New","offer_id":52165308776728,"sku":"9781119282662","price":76.35,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781119282662.jpg?v=1781098182","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/fpga-prototyping-by-systemverilog-examples-xilinx-microblaze-mcs-soc-edition-hardback-9781119282662","provider":"Freshly Printed Books","version":"1.0","type":"link"}