{"product_id":"event-based-neuromorphic-systems-hardback-9780470018491","title":"Event-Based Neuromorphic Systems (Hardback) 9780470018491","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eEvent-Based Neuromorphic Systems\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eShih-Chii Liu (Edited by), SS Liu (Author), Tobi Delbruck (Edited by), Giacomo Indiveri (Edited by), Adrian Whatley (Edited by), Rodney Douglas (Edited by)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780470018491, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 30 January 2015\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e440 pages\u003cbr\u003e25.2 x 17.8 x 2.5 cm, 0.798 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eNeuromorphic electronic engineering takes its inspiration from the functioning of nervous systems to build more power efficient electronic sensors and processors. Event-based neuromorphic systems are inspired by the brain's efficient data-driven communication design, which is key to its quick responses and remarkable capabilities.  This cross-disciplinary text establishes how circuit building blocks are combined in architectures to construct complete systems. These include vision and auditory sensors as well as neuronal processing and learning circuits that implement models of nervous systems.\u003c\/p\u003e \u003cp\u003eTechniques for building multi-chip scalable systems are considered throughout the book, including methods for dealing with transistor mismatch, extensive discussions of communication and interfacing, and making systems that operate in the real world. The book also provides historical context that helps relate the architectures and circuits to each other and that guides readers to the extensive literature. Chapters are written by founding experts and have been extensively edited for overall coherence.\u003c\/p\u003e \u003cp\u003eThis pioneering text is an indispensable resource for practicing neuromorphic electronic engineers, advanced electrical engineering and computer science students and researchers interested in neuromorphic systems.\u003c\/p\u003e \u003cp\u003eKey features:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eSummarises the latest design approaches, applications, and future challenges in the field of neuromorphic engineering.\u003c\/li\u003e \u003cli\u003ePresents examples of practical applications of neuromorphic design principles.\u003c\/li\u003e \u003cli\u003eCovers address-event communication, retinas, cochleas, locomotion, learning theory, neurons, synapses, floating gate circuits, hardware and software infrastructure, algorithms, and future challenges.\u003c\/li\u003e \u003c\/ul\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eList of Contributors xv  \u003cp\u003eForeword xvii\u003c\/p\u003e \u003cp\u003eAcknowledgments xix\u003c\/p\u003e \u003cp\u003eList of Abbreviations and Acronyms xxi\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Origins and Historical Context 3\u003c\/p\u003e \u003cp\u003e1.2 Building Useful Neuromorphic Systems 5\u003c\/p\u003e \u003cp\u003eReferences 5\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart I UNDERSTANDING NEUROMORPHIC SYSTEMS 7\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Communication 9\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Introduction 9\u003c\/p\u003e \u003cp\u003e2.2 Address-Event Representation 12\u003c\/p\u003e \u003cp\u003e2.2.1 AER Encoders 13\u003c\/p\u003e \u003cp\u003e2.2.2 Arbitration Mechanisms 13\u003c\/p\u003e \u003cp\u003e2.2.3 Encoding Mechanisms 17\u003c\/p\u003e \u003cp\u003e2.2.4 Multiple AER Endpoints 19\u003c\/p\u003e \u003cp\u003e2.2.5 Address Mapping 19\u003c\/p\u003e \u003cp\u003e2.2.6 Routing 19\u003c\/p\u003e \u003cp\u003e2.3 Considerations for AER Link Design 20\u003c\/p\u003e \u003cp\u003e2.3.1 Trade-off: Dynamic or Static Allocation 21\u003c\/p\u003e \u003cp\u003e2.3.2 Trade-off: Arbitered Access or Collisions? 23\u003c\/p\u003e \u003cp\u003e2.3.3 Trade-off: Queueing versus Dropping Spikes 24\u003c\/p\u003e \u003cp\u003e2.3.4 Predicting Throughput Requirements 25\u003c\/p\u003e \u003cp\u003e2.3.5 Design Trade-offs 27\u003c\/p\u003e \u003cp\u003e2.4 The Evolution of AER Links 28\u003c\/p\u003e \u003cp\u003e2.4.1 Single Sender, Single Receiver 28\u003c\/p\u003e \u003cp\u003e2.4.2 Multiple Senders, Multiple Receivers 30\u003c\/p\u003e \u003cp\u003e2.4.3 Parallel Signal Protocol 31\u003c\/p\u003e \u003cp\u003e2.4.4 Word-Serial Addressing 32\u003c\/p\u003e \u003cp\u003e2.4.5 Serial Differential Signaling 33\u003c\/p\u003e \u003cp\u003e2.5 Discussion 34\u003c\/p\u003e \u003cp\u003eReferences 35\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Silicon Retinas 37\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction 37\u003c\/p\u003e \u003cp\u003e3.2 Biological Retinas 38\u003c\/p\u003e \u003cp\u003e3.3 Silicon Retinas with Serial Analog Output 39\u003c\/p\u003e \u003cp\u003e3.4 Asynchronous Event-Based Pixel Output Versus Synchronous Frames 40\u003c\/p\u003e \u003cp\u003e3.5 AER Retinas 40\u003c\/p\u003e \u003cp\u003e3.5.1 Dynamic Vision Sensor 41\u003c\/p\u003e \u003cp\u003e3.5.2 Asynchronous Time-Based Image Sensor 46\u003c\/p\u003e \u003cp\u003e3.5.3 Asynchronous Parvo–Magno Retina Model 46\u003c\/p\u003e \u003cp\u003e3.5.4 Event-Based Intensity-Coding Imagers (Octopus and TTFS) 48\u003c\/p\u003e \u003cp\u003e3.5.5 Spatial Contrast and Orientation Vision Sensor (VISe) 50\u003c\/p\u003e \u003cp\u003e3.6 Silicon Retina Pixels 54\u003c\/p\u003e \u003cp\u003e3.6.1 DVS Pixel 54\u003c\/p\u003e \u003cp\u003e3.6.2 ATIS Pixel 56\u003c\/p\u003e \u003cp\u003e3.6.3 VISe Pixel 58\u003c\/p\u003e \u003cp\u003e3.6.4 Octopus Pixel 59\u003c\/p\u003e \u003cp\u003e3.7 New Specifications for Silicon Retinas 60\u003c\/p\u003e \u003cp\u003e3.7.1 DVS Response Uniformity 60\u003c\/p\u003e \u003cp\u003e3.7.2 DVS Background Activity 62\u003c\/p\u003e \u003cp\u003e3.7.3 DVS Dynamic Range 62\u003c\/p\u003e \u003cp\u003e3.7.4 DVS Latency and Jitter 63\u003c\/p\u003e \u003cp\u003e3.8 Discussion 64\u003c\/p\u003e \u003cp\u003eReferences 67\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Silicon Cochleas 71\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction 72\u003c\/p\u003e \u003cp\u003e4.2 Cochlea Architectures 75\u003c\/p\u003e \u003cp\u003e4.2.1 Cascaded 1D 76\u003c\/p\u003e \u003cp\u003e4.2.2 Basic 1D Silicon Cochlea 77\u003c\/p\u003e \u003cp\u003e4.2.3 2D Architecture 78\u003c\/p\u003e \u003cp\u003e4.2.4 The Resistive (Conductive) Network 79\u003c\/p\u003e \u003cp\u003e4.2.5 The BM Resonators 80\u003c\/p\u003e \u003cp\u003e4.2.6 The 2D Silicon Cochlea Model 80\u003c\/p\u003e \u003cp\u003e4.2.7 Adding the Active Nonlinear Behavior of the OHCs 82\u003c\/p\u003e \u003cp\u003e4.3 Spike-Based Cochleas 83\u003c\/p\u003e \u003cp\u003e4.3.1 Q-control of AEREAR2 Filters 85\u003c\/p\u003e \u003cp\u003e4.3.2 Applications: Spike-Based Auditory Processing 86\u003c\/p\u003e \u003cp\u003e4.4 Tree Diagram 87\u003c\/p\u003e \u003cp\u003e4.5 Discussion 87\u003c\/p\u003e \u003cp\u003eReferences 89\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Locomotion Motor Control 91\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 92\u003c\/p\u003e \u003cp\u003e5.1.1 Determining Functional Biological Elements 92\u003c\/p\u003e \u003cp\u003e5.1.2 Rhythmic Motor Patterns 93\u003c\/p\u003e \u003cp\u003e5.2 Modeling Neural Circuits in Locomotor Control 95\u003c\/p\u003e \u003cp\u003e5.2.1 Describing Locomotor Behavior 96\u003c\/p\u003e \u003cp\u003e5.2.2 Fictive Analysis 97\u003c\/p\u003e \u003cp\u003e5.2.3 Connection Models 99\u003c\/p\u003e \u003cp\u003e5.2.4 Basic CPG Construction 100\u003c\/p\u003e \u003cp\u003e5.2.5 Neuromorphic Architectures 102\u003c\/p\u003e \u003cp\u003e5.3 Neuromorphic CPGs at Work 108\u003c\/p\u003e \u003cp\u003e5.3.1 A Neuroprosthesis: Control of Locomotion in Vivo 109\u003c\/p\u003e \u003cp\u003e5.3.2 Walking Robots 111\u003c\/p\u003e \u003cp\u003e5.3.3 Modeling Intersegmental Coordination 112\u003c\/p\u003e \u003cp\u003e5.4 Discussion 113\u003c\/p\u003e \u003cp\u003eReferences 115\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Learning in Neuromorphic Systems 119\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction: Synaptic Connections, Memory, and Learning 120\u003c\/p\u003e \u003cp\u003e6.2 Retaining Memories in Neuromorphic Hardware 121\u003c\/p\u003e \u003cp\u003e6.2.1 The Problem of Memory Maintenance: Intuition 121\u003c\/p\u003e \u003cp\u003e6.2.2 The Problem of Memory Maintenance: Quantitative Analysis 122\u003c\/p\u003e \u003cp\u003e6.2.3 Solving the Problem of Memory Maintenance 124\u003c\/p\u003e \u003cp\u003e6.3 Storing Memories in Neuromorphic Hardware 128\u003c\/p\u003e \u003cp\u003e6.3.1 Synaptic Models for Learning 128\u003c\/p\u003e \u003cp\u003e6.3.2 Implementing a Synaptic Model in Neuromorphic Hardware 132\u003c\/p\u003e \u003cp\u003e6.4 Toward Associative Memories in Neuromorphic Hardware 136\u003c\/p\u003e \u003cp\u003e6.4.1 Memory Retrieval in Attractor Neural Networks 137\u003c\/p\u003e \u003cp\u003e6.4.2 Issues 142\u003c\/p\u003e \u003cp\u003e6.5 Attractor States in a Neuromorphic Chip 143\u003c\/p\u003e \u003cp\u003e6.5.1 Memory Retrieval 143\u003c\/p\u003e \u003cp\u003e6.5.2 Learning Visual Stimuli in Real Time 145\u003c\/p\u003e \u003cp\u003e6.6 Discussion 148\u003c\/p\u003e \u003cp\u003eReferences 149\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart II BUILDING NEUROMORPHIC SYSTEMS 153\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Silicon Neurons 155\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction 156\u003c\/p\u003e \u003cp\u003e7.2 Silicon Neuron Circuit Blocks 158\u003c\/p\u003e \u003cp\u003e7.2.1 Conductance Dynamics 158\u003c\/p\u003e \u003cp\u003e7.2.2 Spike-Event Generation 159\u003c\/p\u003e \u003cp\u003e7.2.3 Spiking Thresholds and Refractory Periods 161\u003c\/p\u003e \u003cp\u003e7.2.4 Spike-Frequency Adaptation and Adaptive Thresholds 162\u003c\/p\u003e \u003cp\u003e7.2.5 Axons and Dendritic Trees 164\u003c\/p\u003e \u003cp\u003e7.2.6 Additional Useful Building Blocks 165\u003c\/p\u003e \u003cp\u003e7.3 Silicon Neuron Implementations 166\u003c\/p\u003e \u003cp\u003e7.3.1 Subthreshold Biophysically Realistic Models 166\u003c\/p\u003e \u003cp\u003e7.3.2 Compact I\u0026amp;F Circuits for Event-Based Systems 169\u003c\/p\u003e \u003cp\u003e7.3.3 Generalized I\u0026amp;F Neuron Circuits 170\u003c\/p\u003e \u003cp\u003e7.3.4 Above Threshold, Accelerated-Time, and Switched-Capacitor Designs 174\u003c\/p\u003e \u003cp\u003e7.4 Discussion 176\u003c\/p\u003e \u003cp\u003eReferences 180\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Silicon Synapses 185\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction 186\u003c\/p\u003e \u003cp\u003e8.2 Silicon Synapse Implementations 188\u003c\/p\u003e \u003cp\u003e8.2.1 Non Conductance-Based Circuits 188\u003c\/p\u003e \u003cp\u003e8.2.2 Conductance-Based Circuits 198\u003c\/p\u003e \u003cp\u003e8.2.3 NMDA Synapse 200\u003c\/p\u003e \u003cp\u003e8.3 Dynamic Plastic Synapses 201\u003c\/p\u003e \u003cp\u003e8.3.1 Short-Term Plasticity 201\u003c\/p\u003e \u003cp\u003e8.3.2 Long-Term Plasticity 203\u003c\/p\u003e \u003cp\u003e8.4 Discussion 213\u003c\/p\u003e \u003cp\u003eReferences 215\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Silicon Cochlea Building Blocks 219\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction 219\u003c\/p\u003e \u003cp\u003e9.2 Voltage-Domain Second-Order Filter 220\u003c\/p\u003e \u003cp\u003e9.2.1 Transconductance Amplifier 220\u003c\/p\u003e \u003cp\u003e9.2.2 Second-Order Low-Pass Filter 222\u003c\/p\u003e \u003cp\u003e9.2.3 Stability of the Filter 223\u003c\/p\u003e \u003cp\u003e9.2.4 Stabilised Second-Order Low-Pass Filter 225\u003c\/p\u003e \u003cp\u003e9.2.5 Differentiation 225\u003c\/p\u003e \u003cp\u003e9.3 Current-Domain Second-Order Filter 227\u003c\/p\u003e \u003cp\u003e9.3.1 The Translinear Loop 227\u003c\/p\u003e \u003cp\u003e9.3.2 Second-Order Tau Cell Log-Domain Filter 229\u003c\/p\u003e \u003cp\u003e9.4 Exponential Bias Generation 230\u003c\/p\u003e \u003cp\u003e9.5 The Inner Hair Cell Model 233\u003c\/p\u003e \u003cp\u003e9.6 Discussion 234\u003c\/p\u003e \u003cp\u003eReferences 234\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Programmable and Configurable Analog Neuromorphic ICs 237\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction 238\u003c\/p\u003e \u003cp\u003e10.2 Floating-Gate Circuit Basics 238\u003c\/p\u003e \u003cp\u003e10.3 Floating-Gate Circuits Enabling Capacitive Circuits 238\u003c\/p\u003e \u003cp\u003e10.4 Modifying Floating-Gate Charge 242\u003c\/p\u003e \u003cp\u003e10.4.1 Electron Tunneling 242\u003c\/p\u003e \u003cp\u003e10.4.2 pFET Hot-Electron Injection 242\u003c\/p\u003e \u003cp\u003e10.5 Accurate Programming of Programmable Analog Devices 244\u003c\/p\u003e \u003cp\u003e10.6 Scaling of Programmable Analog Approaches 246\u003c\/p\u003e \u003cp\u003e10.7 Low-Power Analog Signal Processing 247\u003c\/p\u003e \u003cp\u003e10.8 Low-Power Comparisons to Digital Approaches: Analog Computing in Memory 249\u003c\/p\u003e \u003cp\u003e10.9 Analog Programming at Digital Complexity: Large-Scale Field Programmable Analog Arrays 251\u003c\/p\u003e \u003cp\u003e10.10 Applications of Complex Analog Signal Processing 253\u003c\/p\u003e \u003cp\u003e10.10.1 Analog Transform Imagers 253\u003c\/p\u003e \u003cp\u003e10.10.2 Adaptive Filters and Classifiers 253\u003c\/p\u003e \u003cp\u003e10.11 Discussion 256\u003c\/p\u003e \u003cp\u003eReferences 257\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Bias Generator Circuits 261\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 261\u003c\/p\u003e \u003cp\u003e11.2 Bias Generator Circuits 263\u003c\/p\u003e \u003cp\u003e11.2.1 Bootstrapped Current Mirror Master Bias Current Reference 263\u003c\/p\u003e \u003cp\u003e11.2.2 Master Bias Power Supply Rejection Ratio (PSRR) 265\u003c\/p\u003e \u003cp\u003e11.2.3 Stability of the Master Bias 265\u003c\/p\u003e \u003cp\u003e11.2.4 Master Bias Startup and Power Control 266\u003c\/p\u003e \u003cp\u003e11.2.5 Current Splitters: Obtaining a Digitally Controlled Fraction of the Master Current 267\u003c\/p\u003e \u003cp\u003e11.2.6 Achieving Fine Monotonic Resolution of Bias Currents 271\u003c\/p\u003e \u003cp\u003e11.2.7 Using Coarse–Fine Range Selection 273\u003c\/p\u003e \u003cp\u003e11.2.8 Shifted-Source Biasing for Small Currents 274\u003c\/p\u003e \u003cp\u003e11.2.9 Buffering and Bypass Decoupling of Individual Biases 275\u003c\/p\u003e \u003cp\u003e11.2.10 A General Purpose Bias Buffer Circuit 278\u003c\/p\u003e \u003cp\u003e11.2.11 Protecting Bias Splitter Currents from Parasitic Photocurrents 279\u003c\/p\u003e \u003cp\u003e11.3 Overall Bias Generator Architecture Including External Controller 279\u003c\/p\u003e \u003cp\u003e11.4 Typical Characteristics 280\u003c\/p\u003e \u003cp\u003e11.5 Design Kits 281\u003c\/p\u003e \u003cp\u003e11.6 Discussion 282\u003c\/p\u003e \u003cp\u003eReferences 282\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 On-Chip AER Communication Circuits 285\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction 286\u003c\/p\u003e \u003cp\u003e12.1.1 Communication Cycle 286\u003c\/p\u003e \u003cp\u003e12.1.2 Speedup in Communication 287\u003c\/p\u003e \u003cp\u003e12.2 AER Transmitter Blocks 289\u003c\/p\u003e \u003cp\u003e12.2.1 AER Circuits within a Pixel 289\u003c\/p\u003e \u003cp\u003e12.2.2 Arbiter 290\u003c\/p\u003e \u003cp\u003e12.2.3 Other AER Blocks 295\u003c\/p\u003e \u003cp\u003e12.2.4 Combined Operation 297\u003c\/p\u003e \u003cp\u003e12.3 AER Receiver Blocks 298\u003c\/p\u003e \u003cp\u003e12.3.1 Chip-Level Handshaking Block 298\u003c\/p\u003e \u003cp\u003e12.3.2 Decoder 299\u003c\/p\u003e \u003cp\u003e12.3.3 Handshaking Circuits in Receiver Pixel 300\u003c\/p\u003e \u003cp\u003e12.3.4 Pulse Extender Circuits 301\u003c\/p\u003e \u003cp\u003e12.3.5 Receiver Array Peripheral Handshaking Circuits 301\u003c\/p\u003e \u003cp\u003e12.4 Discussion 302\u003c\/p\u003e \u003cp\u003eReferences 303\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Hardware Infrastructure 305\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Introduction 306\u003c\/p\u003e \u003cp\u003e13.1.1 Monitoring AER Events 307\u003c\/p\u003e \u003cp\u003e13.1.2 Sequencing AER Events 311\u003c\/p\u003e \u003cp\u003e13.1.3 Mapping AER Events 313\u003c\/p\u003e \u003cp\u003e13.2 Hardware Infrastructure Boards for Small Systems 316\u003c\/p\u003e \u003cp\u003e13.2.1 Silicon Cortex 316\u003c\/p\u003e \u003cp\u003e13.2.2 Centralized Communication 317\u003c\/p\u003e \u003cp\u003e13.2.3 Composable Architecture Solution 318\u003c\/p\u003e \u003cp\u003e13.2.4 Daisy-Chain Architecture 324\u003c\/p\u003e \u003cp\u003e13.2.5 Interfacing Boards using Serial AER 324\u003c\/p\u003e \u003cp\u003e13.2.6 Reconfigurable Mesh-Grid Architecture 328\u003c\/p\u003e \u003cp\u003e13.3 Medium-Scale Multichip Systems 329\u003c\/p\u003e \u003cp\u003e13.3.1 Octopus Retina + IFAT 329\u003c\/p\u003e \u003cp\u003e13.3.2 Multichip Orientation System 332\u003c\/p\u003e \u003cp\u003e13.3.3 CAVIAR 335\u003c\/p\u003e \u003cp\u003e13.4 FPGAs 340\u003c\/p\u003e \u003cp\u003e13.5 Discussion 342\u003c\/p\u003e \u003cp\u003eReferences 345\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Software Infrastructure 349\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction 349\u003c\/p\u003e \u003cp\u003e14.1.1 Importance of Cross-Community Commonality 350\u003c\/p\u003e \u003cp\u003e14.2 Chip and System Description Software 350\u003c\/p\u003e \u003cp\u003e14.2.1 Extensible Markup Language 351\u003c\/p\u003e \u003cp\u003e14.2.2 NeuroML 351\u003c\/p\u003e \u003cp\u003e14.3 Configuration Software 352\u003c\/p\u003e \u003cp\u003e14.4 Address Event Stream Handling Software 352\u003c\/p\u003e \u003cp\u003e14.4.1 Field-Programmable Gate Arrays 353\u003c\/p\u003e \u003cp\u003e14.4.2 Structure of AE Stream Handling Software 353\u003c\/p\u003e \u003cp\u003e14.4.3 Bandwidth and Latency 353\u003c\/p\u003e \u003cp\u003e14.4.4 Optimization 354\u003c\/p\u003e \u003cp\u003e14.4.5 Application Programming Interface 355\u003c\/p\u003e \u003cp\u003e14.4.6 Network Transport of AE Streams 355\u003c\/p\u003e \u003cp\u003e14.5 Mapping Software 356\u003c\/p\u003e \u003cp\u003e14.6 Software Examples 357\u003c\/p\u003e \u003cp\u003e14.6.1 ChipDatabase – A System for Tuning Neuromorphic aVLSI Chips 357\u003c\/p\u003e \u003cp\u003e14.6.2 Spike Toolbox 359\u003c\/p\u003e \u003cp\u003e14.6.3 jAER 359\u003c\/p\u003e \u003cp\u003e14.6.4 Python and PyNN 360\u003c\/p\u003e \u003cp\u003e14.7 Discussion 363\u003c\/p\u003e \u003cp\u003eReferences 363\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Algorithmic Processing of Event Streams 365\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Introduction 365\u003c\/p\u003e \u003cp\u003e15.2 Requirements for Software Infrastructure 367\u003c\/p\u003e \u003cp\u003e15.2.1 Processing Latency 369\u003c\/p\u003e \u003cp\u003e15.3 Embedded Implementations 369\u003c\/p\u003e \u003cp\u003e15.4 Examples of Algorithms 370\u003c\/p\u003e \u003cp\u003e15.4.1 Noise Reduction Filters 370\u003c\/p\u003e \u003cp\u003e15.4.2 Time-Stamp Maps and Subsampling by Bit-Shifting Addresses 372\u003c\/p\u003e \u003cp\u003e15.4.3 Event Labelers as Low-Level Feature Detectors 372\u003c\/p\u003e \u003cp\u003e15.4.4 Visual Trackers 374\u003c\/p\u003e \u003cp\u003e15.4.5 Event-Based Audio Processing 378\u003c\/p\u003e \u003cp\u003e15.5 Discussion 379\u003c\/p\u003e \u003cp\u003eReferences 379\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 Towards Large-Scale Neuromorphic Systems 381\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Introduction 381\u003c\/p\u003e \u003cp\u003e16.2 Large-Scale System Examples 382\u003c\/p\u003e \u003cp\u003e16.2.1 Spiking Neural Network Architecture 382\u003c\/p\u003e \u003cp\u003e16.2.2 Hierarchical AER 384\u003c\/p\u003e \u003cp\u003e16.2.3 Neurogrid 386\u003c\/p\u003e \u003cp\u003e16.2.4 High Input Count Analog Neural Network System 388\u003c\/p\u003e \u003cp\u003e16.3 Discussion 390\u003c\/p\u003e \u003cp\u003eReferences 391\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 The Brain as Potential Technology 393\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Introduction 393\u003c\/p\u003e \u003cp\u003e17.2 The Nature of Neuronal Computation: Principles of Brain Technology 395\u003c\/p\u003e \u003cp\u003e17.3 Approaches to Understanding Brains 396\u003c\/p\u003e \u003cp\u003e17.4 Some Principles of Brain Construction and Function 398\u003c\/p\u003e \u003cp\u003e17.5 An Example Model of Neural Circuit Processing 400\u003c\/p\u003e \u003cp\u003e17.6 Toward Neuromorphic Cognition 402\u003c\/p\u003e \u003cp\u003eReferences 404\u003c\/p\u003e \u003cp\u003eIndex 407\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley","offers":[{"title":"Brand New","offer_id":52165915640088,"sku":"9780470018491","price":79.19,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780470018491.jpg?v=1781101811","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/event-based-neuromorphic-systems-hardback-9780470018491","provider":"Freshly Printed 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