{"product_id":"computer-architecture-hardback-9781848214293","title":"Computer Architecture (Hardback) 9781848214293","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eComputer Architecture\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eGérard Blanchet (Author), Bertrand Dupouy (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781848214293, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 18 December 2012\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e380 pages\u003cbr\u003e24 x 16 x 2.7 cm, 0.708 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eThis book lays out the concepts necessary to understand how a computer works.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eFor reasons of clarity, the authors have deliberately chosen examples that apply to machines from all eras, without having to water down the contents of the book. This choice helps to show how techniques, concepts and performances have evolved since the first computers.\u003c\/p\u003e \u003cp\u003eThe book is divided into five parts. The first four, which are of increasing difficulty, are the core of the book: \"Elements of a Basic Architecture\", \"Programming Model and Operation\", \"Memory Hierarchy\", \"Parallelism and Performance Enhancement.\" The final part provides hints and solutions to the exercises in the book as well as appendices. The reader may approach each part independently based on their prior knowledge and goals.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003ci\u003ePreface xiii\u003c\/i\u003e\u003cbr\u003e \u003cbr\u003e \u003cb\u003ePart 1. Elements of a Basic Architecture 1\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e \u003cb\u003eChapter 1. Introduction 3\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  1.1. Historical background 3\u003cbr\u003e \u003cbr\u003e  1.2. Introduction to internal operation 13\u003cbr\u003e \u003cbr\u003e  1.3. Future prospects 15\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2. The Basic Module 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e 2.1. Memory 17\u003cbr\u003e \u003cbr\u003e  2.2. The processor 20\u003cbr\u003e \u003cbr\u003e  2.3. Communication between modules 30\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3. The Representation of Information 35\u003c\/b\u003e\u003cbr\u003e  \u003cbr\u003e  3.1 Review 36\u003cbr\u003e \u003cbr\u003e  3.2. Number representation conventions 38\u003cbr\u003e \u003cbr\u003e  3.3. Character representation 48\u003cbr\u003e \u003cbr\u003e  3.4 Exercises 52\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 2. Programming Model and Operations 55\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4. Instructions 57\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  4.1. Programming model 58\u003cbr\u003e \u003cbr\u003e  4.2 The set of instructions 62\u003cbr\u003e \u003cbr\u003e  4.3. Programming examples 68\u003cbr\u003e \u003cbr\u003e  4.4. From assembly language to basic instructions 70\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5. The Processor 74\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  5.1. The control bus 76\u003cbr\u003e \u003cbr\u003e  5.2. Execution of the instruction 79\u003cbr\u003e \u003cbr\u003e  5.3. Sequencer composition 87\u003cbr\u003e \u003cbr\u003e  5.4. Extensions 91\u003cbr\u003e \u003cbr\u003e  5.5. Exercise 101\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6. Inputs and Outputs 103\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  6.1. Examples 105\u003cbr\u003e \u003cbr\u003e  6.2. Design and addressing of EU 115\u003cbr\u003e \u003cbr\u003e  6.3. Exchange modes 118\u003cbr\u003e \u003cbr\u003e  6.4. Handling interrupts 127\u003cbr\u003e \u003cbr\u003e  6.5. Exercises 133\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 3. Memory Hierarchy 137\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7. Memory 139\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  7.1. The memory resource 139\u003cbr\u003e \u003cbr\u003e  7.2. Characteristics 140\u003cbr\u003e \u003cbr\u003e  7.3. Memory hierarchy 141\u003cbr\u003e \u003cbr\u003e  7.4. Memory size and protection 145\u003cbr\u003e \u003cbr\u003e  7.5. Segmentation 145\u003cbr\u003e \u003cbr\u003e  7.6. Paging 148\u003cbr\u003e \u003cbr\u003e  7.7. Memory interleaving and burst mode 151\u003cbr\u003e \u003cbr\u003e  7.8. Protections, example of the I386 154\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8. Caches 157\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  8.1. Cache memory 157\u003cbr\u003e \u003cbr\u003e  8.2. Replacements algorithms 165\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9. Virtual Memory 175\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  9.1. General concept 176\u003cbr\u003e \u003cbr\u003e  9.2. Rules of the access method 178\u003cbr\u003e \u003cbr\u003e  9.3 Example of the execution of a program 182\u003cbr\u003e \u003cbr\u003e  9.4. Example of two-level paging 188\u003cbr\u003e \u003cbr\u003e  9.5 Paged segmentation 194\u003cbr\u003e \u003cbr\u003e  9.6. Exercise 197\u003cbr\u003e \u003cbr\u003e  9.7. Documentation excerpts 198\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 4. Parallelism and Performance Enhancement 205\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10. Pipeline Architectures 207\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  10.1 Motivations and Ideas 207\u003cbr\u003e \u003cbr\u003e  10.2 Pipeline management problems 212\u003cbr\u003e \u003cbr\u003e  10.3 Handling branches 218\u003cbr\u003e \u003cbr\u003e  10.4 Interrupts and exceptions 233\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11. Example of an Architecture 235\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  11.1 Presentation 235\u003cbr\u003e  \u003cbr\u003e  11.2. Executing an instruction 240\u003cbr\u003e  \u003cbr\u003e  11.3. Conflict resolution in the DLX 246\u003cbr\u003e \u003cbr\u003e  11.4. Exercises 252\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 12. Caches in a Multiprocessor Environment 261\u003c\/b\u003e\u003cbr\u003e  \u003cbr\u003e  12.1. Cache coherence 262\u003cbr\u003e \u003cbr\u003e  12.2. Examples of snooping protocols 267\u003cbr\u003e \u003cbr\u003e  12.3. Improvements 275\u003cbr\u003e \u003cbr\u003e  12.4. Directory-based coherence protocols 275\u003cbr\u003e \u003cbr\u003e  12.5. Consistency 278\u003cbr\u003e \u003cbr\u003e  12.6. Exercises 284\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 13. Superscaler Architectures 287\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  13.1. Superscaler architecture principles 287\u003cbr\u003e \u003cbr\u003e  13.2. Seeking solutions 290\u003cbr\u003e \u003cbr\u003e  13.3. Handling the flow of instructions 295\u003cbr\u003e \u003cbr\u003e  13.4. VLIW architectures 315\u003cbr\u003e \u003cbr\u003e  13.5. Exercises 321\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 5. Appendices 325\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A. Hints and Solutions 327\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  A1.1 The representation of information 327\u003cbr\u003e \u003cbr\u003e  A1.2. The processor 330\u003cbr\u003e \u003cbr\u003e  A1.3. Inputs and outputs 331\u003cbr\u003e \u003cbr\u003e  A1.4. Virtual memory 333\u003cbr\u003e \u003cbr\u003e  A1.5. Pipeline architectures 335\u003cbr\u003e \u003cbr\u003e  A1.6. Caches in a multiprocessor environment 341\u003cbr\u003e \u003cbr\u003e  A1.7. Superscaler architectures 344\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix B. Programming Models 347\u003c\/b\u003e\u003cbr\u003e \u003cbr\u003e  A2.1. Instruction coding in the I8086 347\u003cbr\u003e \u003cbr\u003e  A2.2. Instruction set of the DLX architecture 349\u003c\/p\u003e \u003cp\u003e\u003ci\u003eBibliography 351\u003c\/i\u003e\u003cbr\u003e \u003cbr\u003e \u003ci\u003eIndex 357\u003c\/i\u003e\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Computer hardware [\u003ca title=\"See our other books on Computer hardware\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Computer%20hardware%20%5BUK%5D%22\"\u003eUK\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-ISTE","offers":[{"title":"Brand New","offer_id":52449379057944,"sku":"9781848214293","price":98.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781848214293.jpg?v=1785197358","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/computer-architecture-hardback-9781848214293","provider":"Freshly Printed Books","version":"1.0","type":"link"}