{"product_id":"analysis-and-design-of-analog-integrated-circuits-hardback-9781394220069","title":"Analysis and Design of Analog Integrated Circuits (Hardback) 9781394220069","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eAnalysis and Design of Analog Integrated Circuits\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003ePaul R. Gray (Author), Paul J. Hurst (Author), Stephen H. Lewis (Author), Robert G. Meyer (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781394220069, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 15 February 2024\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e976 pages\u003cbr\u003e26.4 x 19 x 5.1 cm, 1.656 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cb\u003eANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS\u003c\/b\u003e \u003cp\u003e\u003cb\u003eAuthoritative and comprehensive textbook on the fundamentals of analog integrated circuits, with learning aids included throughout\u003c\/b\u003e \u003c\/p\u003e\n\u003cp\u003eWritten in an accessible style to ensure complex content can be appreciated by both students and professionals, this Sixth Edition of \u003ci\u003eAnalysis and Design of Analog Integrated Circuits\u003c\/i\u003e is a highly comprehensive textbook on analog design, offering in-depth coverage of the fundamentals of circuits in a single volume. To aid in reader comprehension and retention, supplementary material includes end of chapter problems, plus a Solution Manual for instructors. \u003c\/p\u003e\n\u003cp\u003eIn addition to the well-established concepts, this Sixth Edition introduces a new super-source follower circuit and its large-signal behavior, frequency response, stability, and noise properties. New material also introduces replica biasing, describes and analyzes two op amps with replica biasing, and provides coverage of weighted zero-value time constants as a method to estimate the location of dominant zeros, pole-zero doublets (including their effect on settling time and three examples of circuits that create doublets), the effect of feedback on pole-zero doublets, and MOS transistor noise performance (including a thorough treatment on thermally induced gate noise). \u003c\/p\u003e\n\u003cp\u003eProviding complete coverage of the subject, \u003ci\u003eAnalysis and Design of Analog Integrated Circuits\u003c\/i\u003e serves as a valuable reference for readers from many different types of backgrounds, including senior undergraduates and first-year graduate students in electrical and computer engineering, along with analog integrated-circuit designers.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eChapter 1 Models for Integrated-Circuit Active Devices 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Introduction 1\u003c\/p\u003e \u003cp\u003e1.2 Depletion Region of a pn Junction 1\u003c\/p\u003e \u003cp\u003e1.2.1 Depletion-Region Capacitance 5\u003c\/p\u003e \u003cp\u003e1.2.2 Junction Breakdown 7\u003c\/p\u003e \u003cp\u003e1.3 Large-Signal Behavior of Bipolar Transistors 9\u003c\/p\u003e \u003cp\u003e1.3.1 Large-Signal Models in the Forward-Active Region 9\u003c\/p\u003e \u003cp\u003e1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region 14\u003c\/p\u003e \u003cp\u003e1.3.3 Saturation and Inverse-Active Regions 16\u003c\/p\u003e \u003cp\u003e1.3.4 Transistor Breakdown Voltages 21\u003c\/p\u003e \u003cp\u003e1.3.5 Dependence of Transistor Current Gain β F on Operating Conditions 24\u003c\/p\u003e \u003cp\u003e1.4 Small-Signal Models of Bipolar Transistors 26\u003c\/p\u003e \u003cp\u003e1.4.1 Transconductance 26\u003c\/p\u003e \u003cp\u003e1.4.2 Base-Charging Capacitance 28\u003c\/p\u003e \u003cp\u003e1.4.3 Input Resistance 29\u003c\/p\u003e \u003cp\u003e1.4.4 Output Resistance 30\u003c\/p\u003e \u003cp\u003e1.4.5 Basic Small-Signal Model of the Bipolar Transistor 30\u003c\/p\u003e \u003cp\u003e1.4.6 Collector-Base Resistance 31\u003c\/p\u003e \u003cp\u003e1.4.7 Parasitic Elements in the Small-Signal Model 31\u003c\/p\u003e \u003cp\u003e1.4.8 Specification of Transistor Frequency Response 35\u003c\/p\u003e \u003cp\u003e1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 39\u003c\/p\u003e \u003cp\u003e1.5.1 Transfer Characteristics of MOS Devices 39\u003c\/p\u003e \u003cp\u003e1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors 46\u003c\/p\u003e \u003cp\u003e1.5.3 Decomposition of Gate-Source Voltage 48\u003c\/p\u003e \u003cp\u003e1.5.4 Threshold Temperature Dependence 48\u003c\/p\u003e \u003cp\u003e1.5.5 MOS Device Voltage Limitations 49\u003c\/p\u003e \u003cp\u003e1.6 Small-Signal Models of MOS Transistors 50\u003c\/p\u003e \u003cp\u003e1.6.1 Transconductance 51\u003c\/p\u003e \u003cp\u003e1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance 52\u003c\/p\u003e \u003cp\u003e1.6.3 Input Resistance 53\u003c\/p\u003e \u003cp\u003e1.6.4 Output Resistance 53\u003c\/p\u003e \u003cp\u003e1.6.5 Basic Small-Signal Model of the MOS Transistor 53\u003c\/p\u003e \u003cp\u003e1.6.6 Body Transconductance 54\u003c\/p\u003e \u003cp\u003e1.6.7 Parasitic Elements in the Small-Signal Model 55\u003c\/p\u003e \u003cp\u003e1.6.8 MOS Transistor Frequency Response 57\u003c\/p\u003e \u003cp\u003e1.7 Short-Channel Effects in MOS Transistors 60\u003c\/p\u003e \u003cp\u003e1.7.1 Velocity Saturation from the Horizontal Field 60\u003c\/p\u003e \u003cp\u003e1.7.2 Transconductance and Transition Frequency 64\u003c\/p\u003e \u003cp\u003e1.7.3 Mobility Degradation from the Vertical Field 66\u003c\/p\u003e \u003cp\u003e1.8 Weak Inversion in MOS Transistors 67\u003c\/p\u003e \u003cp\u003e1.8.1 Drain Current in Weak Inversion 67\u003c\/p\u003e \u003cp\u003e1.8.2 Transconductance and Transition Frequency in Weak Inversion 70\u003c\/p\u003e \u003cp\u003e1.9 Substrate Current Flow in MOS Transistors 73\u003c\/p\u003e \u003cp\u003eA.1.1 Summary of Active-Device Parameters 74\u003c\/p\u003e \u003cp\u003eProblems 76\u003c\/p\u003e \u003cp\u003eReferences 78\u003c\/p\u003e \u003cp\u003eGeneral References 79\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2 Bipolar, MOS, and BiCMOS Integrated-Circuit Technology 81\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Introduction 81\u003c\/p\u003e \u003cp\u003e2.2 Basic Processes in Integrated-Circuit Fabrication 82\u003c\/p\u003e \u003cp\u003e2.2.1 Electrical Resistivity of Silicon 82\u003c\/p\u003e \u003cp\u003e2.2.2 Solid-State Diffusion 83\u003c\/p\u003e \u003cp\u003e2.2.3 Electrical Properties of Diffused Layers 85\u003c\/p\u003e \u003cp\u003e2.2.4 Photolithography 87\u003c\/p\u003e \u003cp\u003e2.2.5 Epitaxial Growth 89\u003c\/p\u003e \u003cp\u003e2.2.6 Ion Implantation 90\u003c\/p\u003e \u003cp\u003e2.2.7 Local Oxidation 90\u003c\/p\u003e \u003cp\u003e2.2.8 Polysilicon Deposition 90\u003c\/p\u003e \u003cp\u003e2.3 High-Voltage Bipolar Integrated-Circuit Fabrication 91\u003c\/p\u003e \u003cp\u003e2.4 Advanced Bipolar Integrated-Circuit Fabrication 95\u003c\/p\u003e \u003cp\u003e2.5 Active Devices in Bipolar Analog Integrated Circuits 98\u003c\/p\u003e \u003cp\u003e2.5.1 Integrated-Circuit npn Transistors 99\u003c\/p\u003e \u003cp\u003e2.5.2 Integrated-Circuit pnp Transistors 111\u003c\/p\u003e \u003cp\u003e2.6 Passive Components in Bipolar Integrated Circuits 118\u003c\/p\u003e \u003cp\u003e2.6.1 Diffused Resistors 119\u003c\/p\u003e \u003cp\u003e2.6.2 Epitaxial and Epitaxial-Pinch Resistors 122\u003c\/p\u003e \u003cp\u003e2.6.3 Integrated-Circuit Capacitors 124\u003c\/p\u003e \u003cp\u003e2.6.4 Zener Diodes 124\u003c\/p\u003e \u003cp\u003e2.6.5 Junction Diodes 125\u003c\/p\u003e \u003cp\u003e2.7 Modifications to the Basic Bipolar Process 127\u003c\/p\u003e \u003cp\u003e2.7.1 Dielectric Isolation 127\u003c\/p\u003e \u003cp\u003e2.7.2 Compatible Processing for High-Performance Active Devices 128\u003c\/p\u003e \u003cp\u003e2.7.3 High-Performance Passive Components 131\u003c\/p\u003e \u003cp\u003e2.8 MOS Integrated-Circuit Fabrication 131\u003c\/p\u003e \u003cp\u003e2.9 Active Devices in MOS Integrated Circuits 135\u003c\/p\u003e \u003cp\u003e2.9.1 n-Channel Transistors 135\u003c\/p\u003e \u003cp\u003e2.9.2 p-Channel Transistors 148\u003c\/p\u003e \u003cp\u003e2.9.3 Depletion Devices 148\u003c\/p\u003e \u003cp\u003e2.9.4 Bipolar Transistors 149\u003c\/p\u003e \u003cp\u003e2.10 Passive Components in MOS Technology 150\u003c\/p\u003e \u003cp\u003e2.10.1 Resistors 150\u003c\/p\u003e \u003cp\u003e2.10.2 Capacitors in MOS Technology 152\u003c\/p\u003e \u003cp\u003e2.10.3 Latchup in CMOS Technology 155\u003c\/p\u003e \u003cp\u003e2.11 BiCMOS Technology 156\u003c\/p\u003e \u003cp\u003e2.12 Heterojunction Bipolar Transistors 157\u003c\/p\u003e \u003cp\u003e2.13 Interconnect Delay 160\u003c\/p\u003e \u003cp\u003e2.14 Economics of Integrated-Circuit Fabrication 160\u003c\/p\u003e \u003cp\u003e2.14.1 Yield Considerations in Integrated-Circuit Fabrication 161\u003c\/p\u003e \u003cp\u003e2.14.2 Cost Considerations in Integrated-Circuit Fabrication 163\u003c\/p\u003e \u003cp\u003eA.2.1 Spice Model-Parameter Files 166\u003c\/p\u003e \u003cp\u003eProblems 167\u003c\/p\u003e \u003cp\u003eReferences 170\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3 Single-Transistor and Multiple-Transistor Amplifiers 173\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Device Model Selection for Approximate Analysis of Analog Circuits 174\u003c\/p\u003e \u003cp\u003e3.2 Two-Port Modeling of Amplifiers 175\u003c\/p\u003e \u003cp\u003e3.3 Basic Single-Transistor Amplifier Stages 177\u003c\/p\u003e \u003cp\u003e3.3.1 Common-Emitter Configuration 178\u003c\/p\u003e \u003cp\u003e3.3.2 Common-Source Configuration 182\u003c\/p\u003e \u003cp\u003e3.3.3 Common-Base Configuration 186\u003c\/p\u003e \u003cp\u003e3.3.4 Common-Gate Configuration 189\u003c\/p\u003e \u003cp\u003e3.3.5 Common-Base and Common-Gate Configurations with Finite r o 191\u003c\/p\u003e \u003cp\u003e3.3.6 Common-Collector Configuration (Emitter Follower) 195\u003c\/p\u003e \u003cp\u003e3.3.7 Common-Drain Configuration (Source Follower) 198\u003c\/p\u003e \u003cp\u003e3.3.8 Common-Emitter Amplifier with Emitter Degeneration 201\u003c\/p\u003e \u003cp\u003e3.3.9 Common-Source Amplifier with Source Degeneration 204\u003c\/p\u003e \u003cp\u003e3.4 Multiple-Transistor Amplifier Stages 206\u003c\/p\u003e \u003cp\u003e3.4.1 The CC-CE, CC-CC, and Darlington Configurations 206\u003c\/p\u003e \u003cp\u003e3.4.2 The Cascode Configuration 210\u003c\/p\u003e \u003cp\u003e3.4.3 The Active Cascode 214\u003c\/p\u003e \u003cp\u003e3.4.4 The Super Source Follower 216\u003c\/p\u003e \u003cp\u003e3.5 Differential Pairs 219\u003c\/p\u003e \u003cp\u003e3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair 219\u003c\/p\u003e \u003cp\u003e3.5.2 The dc Transfer Characteristic with Emitter Degeneration 221\u003c\/p\u003e \u003cp\u003e3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair 222\u003c\/p\u003e \u003cp\u003e3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers 225\u003c\/p\u003e \u003cp\u003e3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers 228\u003c\/p\u003e \u003cp\u003e3.5.6 Device Mismatch Effects in Differential Amplifiers 235\u003c\/p\u003e \u003cp\u003eA.3.1 Elementary Statistics and the Gaussian Distribution 250\u003c\/p\u003e \u003cp\u003eProblems 253\u003c\/p\u003e \u003cp\u003eReferences 257\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4 Current Mirrors, Active Loads, and References 259\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction 259\u003c\/p\u003e \u003cp\u003e4.2 Replica Biasing 259\u003c\/p\u003e \u003cp\u003e4.3 Current Mirrors 261\u003c\/p\u003e \u003cp\u003e4.3.1 General Properties 261\u003c\/p\u003e \u003cp\u003e4.3.2 Simple Current Mirror 263\u003c\/p\u003e \u003cp\u003e4.3.3 Simple Current Mirror with Beta Helper 269\u003c\/p\u003e \u003cp\u003e4.3.4 Simple Current Mirror with Degeneration 270\u003c\/p\u003e \u003cp\u003e4.3.5 Cascode Current Mirror 272\u003c\/p\u003e \u003cp\u003e4.3.6 Wilson Current Mirror 283\u003c\/p\u003e \u003cp\u003e4.4 Active Loads 287\u003c\/p\u003e \u003cp\u003e4.4.1 Motivation 287\u003c\/p\u003e \u003cp\u003e4.4.2 Common-Emitter–Common-Source Amplifier with Complementary Load 288\u003c\/p\u003e \u003cp\u003e4.4.3 Common-Emitter–Common-Source Amplifier with Depletion Load 291\u003c\/p\u003e \u003cp\u003e4.4.4 Common-Emitter–Common-Source Amplifier with Diode-Connected Load 293\u003c\/p\u003e \u003cp\u003e4.4.5 Differential Pair with Current-Mirror Load 296\u003c\/p\u003e \u003cp\u003e4.5 Voltage and Current References 309\u003c\/p\u003e \u003cp\u003e4.5.1 Low-Current Biasing 309\u003c\/p\u003e \u003cp\u003e4.5.2 Supply-Insensitive Biasing 315\u003c\/p\u003e \u003cp\u003e4.5.3 Temperature-Insensitive Biasing 327\u003c\/p\u003e \u003cp\u003eA.4.1 Matching Considerations in Current Mirrors 338\u003c\/p\u003e \u003cp\u003eA.4.1.1 Bipolar 338\u003c\/p\u003e \u003cp\u003eA.4.1.2 Mos 340\u003c\/p\u003e \u003cp\u003eA.4.2 Input Offset Voltage of a Differential Pair with Active Load 343\u003c\/p\u003e \u003cp\u003eA.4.2.1 Bipolar 343\u003c\/p\u003e \u003cp\u003eA.4.2.2 Mos 345\u003c\/p\u003e \u003cp\u003eProblems 348\u003c\/p\u003e \u003cp\u003eReferences 353\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5 Output Stages 355\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 355\u003c\/p\u003e \u003cp\u003e5.2 The Emitter Follower as an Output Stage 355\u003c\/p\u003e \u003cp\u003e5.2.1 Transfer Characteristics of the Emitter-Follower 356\u003c\/p\u003e \u003cp\u003e5.2.2 Power Output and Efficiency 359\u003c\/p\u003e \u003cp\u003e5.2.3 Emitter-Follower Drive Requirements 366\u003c\/p\u003e \u003cp\u003e5.2.4 Small-Signal Properties of the Emitter Follower 366\u003c\/p\u003e \u003cp\u003e5.3 The Source Follower as an Output Stage 368\u003c\/p\u003e \u003cp\u003e5.3.1 Transfer Characteristics of the Source Follower 368\u003c\/p\u003e \u003cp\u003e5.3.2 Distortion in the Source Follower 370\u003c\/p\u003e \u003cp\u003e5.3.3 Transfer Characteristics of the Super Source Follower 374\u003c\/p\u003e \u003cp\u003e5.4 Class B Push–Pull Output Stage 378\u003c\/p\u003e \u003cp\u003e5.4.1 Transfer Characteristic of the Class B Stage 378\u003c\/p\u003e \u003cp\u003e5.4.2 Power Output and Efficiency of the Class B Stage 381\u003c\/p\u003e \u003cp\u003e5.4.3 Practical Realizations of Class B Complementary Output Stages 385\u003c\/p\u003e \u003cp\u003e5.4.4 All-npn Class B Output Stage 392\u003c\/p\u003e \u003cp\u003e5.4.5 Quasi-Complementary Output Stages 394\u003c\/p\u003e \u003cp\u003e5.4.6 Overload Protection 397\u003c\/p\u003e \u003cp\u003e5.5 CMOS Class AB Output Stages 399\u003c\/p\u003e \u003cp\u003e5.5.1 Common-Drain Configuration 399\u003c\/p\u003e \u003cp\u003e5.5.2 Common-Source Configuration with Error Amplifiers 401\u003c\/p\u003e \u003cp\u003e5.5.3 Alternative Configurations 408\u003c\/p\u003e \u003cp\u003eProblems 415\u003c\/p\u003e \u003cp\u003eReferences 420\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6 Operational Amplifiers with Single-Ended Outputs 421\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Applications of Operational Amplifiers 422\u003c\/p\u003e \u003cp\u003e6.1.1 Basic Feedback Concepts 422\u003c\/p\u003e \u003cp\u003e6.1.2 Inverting Amplifier 423\u003c\/p\u003e \u003cp\u003e6.1.3 Noninverting Amplifier 425\u003c\/p\u003e \u003cp\u003e6.1.4 Differential Amplifier 425\u003c\/p\u003e \u003cp\u003e6.1.5 Nonlinear Analog Operations 426\u003c\/p\u003e \u003cp\u003e6.1.6 Integrator, Differentiator 427\u003c\/p\u003e \u003cp\u003e6.1.7 Internal Amplifiers 428\u003c\/p\u003e \u003cp\u003e6.2 Deviations from Ideality in Real Operational Amplifiers 436\u003c\/p\u003e \u003cp\u003e6.2.1 Input Bias Current 437\u003c\/p\u003e \u003cp\u003e6.2.2 Input Offset Current 437\u003c\/p\u003e \u003cp\u003e6.2.3 Input Offset Voltage 438\u003c\/p\u003e \u003cp\u003e6.2.4 Common-Mode Input Range 438\u003c\/p\u003e \u003cp\u003e6.2.5 Common-Mode Rejection Ratio (cmrr) 439\u003c\/p\u003e \u003cp\u003e6.2.6 Power-Supply Rejection Ratio (psrr) 440\u003c\/p\u003e \u003cp\u003e6.2.7 Input Resistance 441\u003c\/p\u003e \u003cp\u003e6.2.8 Output Resistance 442\u003c\/p\u003e \u003cp\u003e6.2.9 Frequency Response 442\u003c\/p\u003e \u003cp\u003e6.2.10 Operational-Amplifier Equivalent Circuit 442\u003c\/p\u003e \u003cp\u003e6.3 Basic Two-Stage MOS Operational Amplifiers 443\u003c\/p\u003e \u003cp\u003e6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain 444\u003c\/p\u003e \u003cp\u003e6.3.2 Output Swing 446\u003c\/p\u003e \u003cp\u003e6.3.3 Input Offset Voltage 446\u003c\/p\u003e \u003cp\u003e6.3.4 Common-Mode Rejection Ratio 450\u003c\/p\u003e \u003cp\u003e6.3.5 Common-Mode Input Range 451\u003c\/p\u003e \u003cp\u003e6.3.6 Power-Supply Rejection Ratio (psrr) 453\u003c\/p\u003e \u003cp\u003e6.3.7 Effect of Overdrive Voltages 458\u003c\/p\u003e \u003cp\u003e6.3.8 Layout Considerations 459\u003c\/p\u003e \u003cp\u003e6.3.9 Amplifier with Level Shifting in the Input Stage 462\u003c\/p\u003e \u003cp\u003e6.4 Two-Stage MOS Operational Amplifiers with Cascodes 465\u003c\/p\u003e \u003cp\u003e6.5 MOS Folded-Cascode Operational Amplifiers 467\u003c\/p\u003e \u003cp\u003e6.6 MOS Telescopic-Cascode Operational Amplifiers 471\u003c\/p\u003e \u003cp\u003e6.7 Replica Biasing of the Tail Current Source 475\u003c\/p\u003e \u003cp\u003e6.8 MOS Active-Cascode Operational Amplifiers 489\u003c\/p\u003e \u003cp\u003eProblems 492\u003c\/p\u003e \u003cp\u003eReferences 498\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7 Frequency Response of Integrated Circuits 499\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction 499\u003c\/p\u003e \u003cp\u003e7.2 Single-Stage Amplifiers 499\u003c\/p\u003e \u003cp\u003e7.2.1 Single-Stage Voltage Amplifiers and the Miller Effect 499\u003c\/p\u003e \u003cp\u003e7.2.2 Frequency Response of the Common-Mode Gain for a Differential Amplifier 511\u003c\/p\u003e \u003cp\u003e7.2.3 Frequency Response of Voltage Buffers 513\u003c\/p\u003e \u003cp\u003e7.2.4 Frequency Response of Current Buffers 527\u003c\/p\u003e \u003cp\u003e7.3 Multistage Amplifier Frequency Response 531\u003c\/p\u003e \u003cp\u003e7.3.1 Dominant-Pole Approximation 531\u003c\/p\u003e \u003cp\u003e7.3.2 Zero-Value Time Constant Analysis 532\u003c\/p\u003e \u003cp\u003e7.3.3 Cascade Voltage-Amplifier Frequency Response 537\u003c\/p\u003e \u003cp\u003e7.3.4 Cascode Frequency Response 541\u003c\/p\u003e \u003cp\u003e7.3.5 Frequency Response of a Current Mirror Loading a Differential Pair 548\u003c\/p\u003e \u003cp\u003e7.3.6 Short-Circuit Time Constants 549\u003c\/p\u003e \u003cp\u003e7.3.7 Weighted Zero-Value Time Constants 554\u003c\/p\u003e \u003cp\u003e7.4 Relation Between Frequency Response and Time Response 563\u003c\/p\u003e \u003cp\u003e7.5 Pole-Zero Doublets 565\u003c\/p\u003e \u003cp\u003e7.5.1 Effect of a Pole-Zero Doublet on Settling Time 565\u003c\/p\u003e \u003cp\u003e7.5.2 Frequency Dependence of a Cascode Current-Source Load 570\u003c\/p\u003e \u003cp\u003e7.5.3 Frequency Dependence of an Active-Cascode Current-Source Load 572\u003c\/p\u003e \u003cp\u003e7.5.4 Doublet in a Differential Amplifier with Mismatch 574\u003c\/p\u003e \u003cp\u003eProblems 575\u003c\/p\u003e \u003cp\u003eReferences 584\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8 Feedback 585\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Ideal Feedback Equation 585\u003c\/p\u003e \u003cp\u003e8.2 Gain Sensitivity 587\u003c\/p\u003e \u003cp\u003e8.3 Effect of Negative Feedback on Distortion 587\u003c\/p\u003e \u003cp\u003e8.4 Feedback Configurations 589\u003c\/p\u003e \u003cp\u003e8.4.1 Series-Shunt Feedback 589\u003c\/p\u003e \u003cp\u003e8.4.2 Shunt-Shunt Feedback 592\u003c\/p\u003e \u003cp\u003e8.4.3 Shunt-Series Feedback 594\u003c\/p\u003e \u003cp\u003e8.4.4 Series-Series Feedback 595\u003c\/p\u003e \u003cp\u003e8.5 Practical Configurations and the Effect of Loading 595\u003c\/p\u003e \u003cp\u003e8.5.1 Shunt-Shunt Feedback 596\u003c\/p\u003e \u003cp\u003e8.5.2 Series-Series Feedback 602\u003c\/p\u003e \u003cp\u003e8.5.3 Series-Shunt Feedback 611\u003c\/p\u003e \u003cp\u003e8.5.4 Shunt-Series Feedback 617\u003c\/p\u003e \u003cp\u003e8.5.5 Summary 620\u003c\/p\u003e \u003cp\u003e8.6 Single-Stage Feedback 620\u003c\/p\u003e \u003cp\u003e8.6.1 Local Series-Series Feedback 622\u003c\/p\u003e \u003cp\u003e8.6.2 Local Series-Shunt Feedback 624\u003c\/p\u003e \u003cp\u003e8.7 The Voltage Regulator as a Feedback Circuit 626\u003c\/p\u003e \u003cp\u003e8.8 Feedback Circuit Analysis Using the Return Ratio 632\u003c\/p\u003e \u003cp\u003e8.8.1 Closed-Loop Gain Using the Return Ratio 634\u003c\/p\u003e \u003cp\u003e8.8.2 Closed-Loop Impedance Formula Using the Return Ratio 640\u003c\/p\u003e \u003cp\u003e8.8.3 Summary—Return-Ratio Analysis 646\u003c\/p\u003e \u003cp\u003e8.9 Modeling Input and Output Ports in Feedback Circuits 646\u003c\/p\u003e \u003cp\u003eProblems 649\u003c\/p\u003e \u003cp\u003eReferences 656\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9 Frequency Response and Stability of Feedback Amplifiers 657\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction 657\u003c\/p\u003e \u003cp\u003e9.2 Relation Between Gain and Bandwidth in Feedback Amplifiers 657\u003c\/p\u003e \u003cp\u003e9.3 Instability 659\u003c\/p\u003e \u003cp\u003e9.3.1 The Nyquist Criterion 659\u003c\/p\u003e \u003cp\u003e9.3.2 Phase Margin and Gain Margin 661\u003c\/p\u003e \u003cp\u003e9.3.3 Stability of the Super Source Follower 666\u003c\/p\u003e \u003cp\u003e9.4 Compensation 671\u003c\/p\u003e \u003cp\u003e9.4.1 Theory of Compensation 671\u003c\/p\u003e \u003cp\u003e9.4.2 Methods of Compensation 676\u003c\/p\u003e \u003cp\u003e9.4.3 Two-Stage MOS Amplifier Compensation 681\u003c\/p\u003e \u003cp\u003e9.4.4 Compensation of Single-Stage CMOS Op Amps 693\u003c\/p\u003e \u003cp\u003e9.4.5 Nested Miller Compensation 696\u003c\/p\u003e \u003cp\u003e9.5 Root-Locus Techniques 705\u003c\/p\u003e \u003cp\u003e9.5.1 Root Locus for a Three-Pole Transfer Function 705\u003c\/p\u003e \u003cp\u003e9.5.2 Rules for Root-Locus Construction 708\u003c\/p\u003e \u003cp\u003e9.5.3 Root Locus for Dominant-Pole Compensation 718\u003c\/p\u003e \u003cp\u003e9.5.4 Root Locus for Feedback-Zero Compensation 719\u003c\/p\u003e \u003cp\u003e9.6 Slew Rate 723\u003c\/p\u003e \u003cp\u003e9.6.1 Origin of Slew-Rate Limitations 723\u003c\/p\u003e \u003cp\u003e9.6.2 Methods of Improving Slew Rate in Two-Stage Op Amps 725\u003c\/p\u003e \u003cp\u003e9.6.3 Improving Slew Rate in Bipolar Op Amps 728\u003c\/p\u003e \u003cp\u003e9.6.4 Improving Slew Rate in MOS Op Amps 729\u003c\/p\u003e \u003cp\u003e9.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance 733\u003c\/p\u003e \u003cp\u003e9.7 Effect of Feedback on a Pole-Zero Doublet 734\u003c\/p\u003e \u003cp\u003eA.9.1 Analysis in Terms of Return-Ratio Parameters 736\u003c\/p\u003e \u003cp\u003eA.9.2 Roots of a Quadratic Equation 737\u003c\/p\u003e \u003cp\u003eProblems 739\u003c\/p\u003e \u003cp\u003eReferences 746\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10 Nonlinear Analog Circuits 747\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction 747\u003c\/p\u003e \u003cp\u003e10.2 Analog Multipliers Employing the Bipolar Transistor 747\u003c\/p\u003e \u003cp\u003e10.2.1 The Emitter-Coupled Pair as a Simple Multiplier 748\u003c\/p\u003e \u003cp\u003e10.2.2 The dc Analysis of the Gilbert Multiplier Cell 750\u003c\/p\u003e \u003cp\u003e10.2.3 The Gilbert Cell as an Analog Multiplier 752\u003c\/p\u003e \u003cp\u003e10.2.4 A Complete Analog Multiplier 755\u003c\/p\u003e \u003cp\u003e10.2.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector 756\u003c\/p\u003e \u003cp\u003e10.3 Phase-Locked Loops 760\u003c\/p\u003e \u003cp\u003e10.3.1 Phase-Locked Loop Concepts 760\u003c\/p\u003e \u003cp\u003e10.3.2 The Phase-Locked Loop in the Locked Condition 762\u003c\/p\u003e \u003cp\u003e10.3.3 Integrated-Circuit Phase-Locked Loops 771\u003c\/p\u003e \u003cp\u003e10.4 Nonlinear Function Synthesis 775\u003c\/p\u003e \u003cp\u003eProblems 777\u003c\/p\u003e \u003cp\u003eReferences 779\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11 Noise in Integrated Circuits 781\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 781\u003c\/p\u003e \u003cp\u003e11.2 Sources of Noise 781\u003c\/p\u003e \u003cp\u003e11.2.1 Shot Noise 781\u003c\/p\u003e \u003cp\u003e11.2.2 Thermal Noise 785\u003c\/p\u003e \u003cp\u003e11.2.3 Flicker Noise (1\/f Noise) 786\u003c\/p\u003e \u003cp\u003e11.2.4 Burst Noise (Popcorn Noise) 787\u003c\/p\u003e \u003cp\u003e11.2.5 Avalanche Noise 787\u003c\/p\u003e \u003cp\u003e11.3 Noise Models of Integrated-Circuit Components 789\u003c\/p\u003e \u003cp\u003e11.3.1 Junction Diode 789\u003c\/p\u003e \u003cp\u003e11.3.2 Bipolar Transistor 790\u003c\/p\u003e \u003cp\u003e11.3.3 MOS Transistor 791\u003c\/p\u003e \u003cp\u003e11.3.4 Resistors 798\u003c\/p\u003e \u003cp\u003e11.3.5 Capacitors and Inductors 799\u003c\/p\u003e \u003cp\u003e11.4 Circuit Noise Calculations 799\u003c\/p\u003e \u003cp\u003e11.4.1 Bipolar Transistor Noise Performance 802\u003c\/p\u003e \u003cp\u003e11.4.2 Equivalent Input Noise and the Minimum Detectable Signal 805\u003c\/p\u003e \u003cp\u003e11.4.3 MOS Transistor Noise Performance 807\u003c\/p\u003e \u003cp\u003e11.5 Equivalent Input Noise Generators 812\u003c\/p\u003e \u003cp\u003e11.5.1 Bipolar Transistor Noise Generators 813\u003c\/p\u003e \u003cp\u003e11.5.2 MOS Transistor Noise Generators 818\u003c\/p\u003e \u003cp\u003e11.6 Effect of Feedback on Noise Performance 820\u003c\/p\u003e \u003cp\u003e11.6.1 Effect of Ideal Feedback on Noise Performance 821\u003c\/p\u003e \u003cp\u003e11.6.2 Effect of Practical Feedback on Noise Performance 821\u003c\/p\u003e \u003cp\u003e11.7 Noise Performance of Other Transistor Configurations 828\u003c\/p\u003e \u003cp\u003e11.7.1 Common-Base-Stage Noise Performance 828\u003c\/p\u003e \u003cp\u003e11.7.2 Emitter-Follower Noise Performance 829\u003c\/p\u003e \u003cp\u003e11.7.3 Differential-Pair Noise Performance 830\u003c\/p\u003e \u003cp\u003e11.7.4 Super-Source-Follower Noise Performance 833\u003c\/p\u003e \u003cp\u003e11.8 Noise in Operational Amplifiers 836\u003c\/p\u003e \u003cp\u003e11.9 Noise Bandwidth 840\u003c\/p\u003e \u003cp\u003e11.10 Noise Figure and Noise Temperature 845\u003c\/p\u003e \u003cp\u003e11.10.1 Noise Figure 845\u003c\/p\u003e \u003cp\u003e11.10.2 Noise Temperature 849\u003c\/p\u003e \u003cp\u003eProblems 849\u003c\/p\u003e \u003cp\u003eReferences 854\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 12 Fully Differential Operational Amplifiers 857\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction 857\u003c\/p\u003e \u003cp\u003e12.2 Properties of Fully Differential Amplifiers 857\u003c\/p\u003e \u003cp\u003e12.3 Small-Signal Models for Balanced Differential Amplifiers 860\u003c\/p\u003e \u003cp\u003e12.4 Common-Mode Feedback 865\u003c\/p\u003e \u003cp\u003e12.4.1 Common-Mode Feedback at Low Frequencies 867\u003c\/p\u003e \u003cp\u003e12.4.2 Stability and Compensation Considerations in a CMFB Loop 871\u003c\/p\u003e \u003cp\u003e12.5 CMFB Circuits 873\u003c\/p\u003e \u003cp\u003e12.5.1 CMFB Using Resistive Divider and Amplifier 873\u003c\/p\u003e \u003cp\u003e12.5.2 CMFB Using Two Differential Pairs 878\u003c\/p\u003e \u003cp\u003e12.5.3 CMFB Using Transistors in the Triode Region 880\u003c\/p\u003e \u003cp\u003e12.5.4 Switched-Capacitor CMFB 882\u003c\/p\u003e \u003cp\u003e12.6 Fully Differential Op Amps 885\u003c\/p\u003e \u003cp\u003e12.6.1 A Fully Differential Two-Stage Op Amp 885\u003c\/p\u003e \u003cp\u003e12.6.2 Fully Differential Telescopic-Cascode Op Amp 896\u003c\/p\u003e \u003cp\u003e12.6.3 Fully Differential Folded-Cascode Op Amp 897\u003c\/p\u003e \u003cp\u003e12.6.4 A Differential Op Amp with Two Differential Input Stages 898\u003c\/p\u003e \u003cp\u003e12.6.5 Neutralization 899\u003c\/p\u003e \u003cp\u003e12.7 Unbalanced Fully Differential Circuits 901\u003c\/p\u003e \u003cp\u003e12.8 Bandwidth of the CMFB Loop 907\u003c\/p\u003e \u003cp\u003e12.9 Analysis of a CMOS Fully Differential Folded-Cascode Op Amp 909\u003c\/p\u003e \u003cp\u003e12.9.1 dc Biasing 911\u003c\/p\u003e \u003cp\u003e12.9.2 Low-Frequency Analysis 914\u003c\/p\u003e \u003cp\u003e12.9.3 Frequency and Time Responses in a Feedback Application 920\u003c\/p\u003e \u003cp\u003eProblems 927\u003c\/p\u003e \u003cp\u003eReferences 933\u003c\/p\u003e \u003cp\u003eIndex 935\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley","offers":[{"title":"Brand New","offer_id":52173730447640,"sku":"9781394220069","price":84.39,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781394220069.jpg?v=1781168882","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/analysis-and-design-of-analog-integrated-circuits-hardback-9781394220069","provider":"Freshly Printed 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