{"product_id":"analog-integrated-circuit-design-international-student-version-paperback-softback-9781118092330","title":"Analog Integrated Circuit Design, International Student Version (Paperback \/ softback) 9781118092330","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eAnalog Integrated Circuit Design, International Student Version\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eTony Chan Carusone (Author), David A. Johns (Author), Kenneth W. Martin (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9781118092330, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003ePaperback \/ softback, published 11 May 2012\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e832 pages\u003cbr\u003e23.6 x 19.1 x 2.6 cm, 1.198 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e\u003cp\u003eWhen first published this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated but continues the central themes of the first edition which made it so sucessful.\u003c\/p\u003e \u003cp\u003eThis edition features extensive new material on CMOS IC device modeling, processing and layout.  Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A\/D converters.  Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers. \u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003e\u003cb\u003eCHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Semiconductors and pn Junctions 1\u003c\/p\u003e \u003cp\u003e1.1.1 Diodes 2\u003c\/p\u003e \u003cp\u003e1.1.2 Reverse-Biased Diodes 4\u003c\/p\u003e \u003cp\u003e1.1.3 Graded Junctions 8\u003c\/p\u003e \u003cp\u003e1.1.4 Large-Signal Junction Capacitance 10\u003c\/p\u003e \u003cp\u003e1.1.5 Forward-Biased Junctions 11\u003c\/p\u003e \u003cp\u003e1.1.6 Junction Capacitance of Forward-Biased Diode 12\u003c\/p\u003e \u003cp\u003e1.1.7 Small-Signal Model of a Forward-Biased Diode 13\u003c\/p\u003e \u003cp\u003e1.1.8 Schottky Diodes 14\u003c\/p\u003e \u003cp\u003e1.2 MOS Transistors 15\u003c\/p\u003e \u003cp\u003e1.2.1 Symbols for MOS Transistors 16\u003c\/p\u003e \u003cp\u003e1.2.2 Basic Operation 17\u003c\/p\u003e \u003cp\u003e1.2.3 Large-Signal Modelling 22\u003c\/p\u003e \u003cp\u003e1.2.4 Body Effect 25\u003c\/p\u003e \u003cp\u003e1.2.5 p-Channel Transistors 26\u003c\/p\u003e \u003cp\u003e1.2.6 Low-Frequency Small-Signal Modelling in the Active Region 26\u003c\/p\u003e \u003cp\u003e1.2.7 High-Frequency Small-Signal Modelling in the Active Region 32\u003c\/p\u003e \u003cp\u003e1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions 35\u003c\/p\u003e \u003cp\u003e1.2.9 Analog Figures of Merit and Trade-offs 37\u003c\/p\u003e \u003cp\u003e1.3 Device Model Summary 39\u003c\/p\u003e \u003cp\u003e1.3.1 Constants 40\u003c\/p\u003e \u003cp\u003e1.3.2 Diode Equations 40\u003c\/p\u003e \u003cp\u003e1.3.3 MOS Transistor Equations 41\u003c\/p\u003e \u003cp\u003e1.4 Advanced MOS Modelling 43\u003c\/p\u003e \u003cp\u003e1.4.1 Subthreshold Operation 43\u003c\/p\u003e \u003cp\u003e1.4.2 Mobility Degradation 46\u003c\/p\u003e \u003cp\u003e1.4.3 Summary of Subthreshold and Mobility Degradation Equations 48\u003c\/p\u003e \u003cp\u003e1.4.4 Parasitic Resistances 48\u003c\/p\u003e \u003cp\u003e1.4.5 Short-Channel Effects 49\u003c\/p\u003e \u003cp\u003e1.4.6 Leakage Currents 50\u003c\/p\u003e \u003cp\u003e1.5 SPICE Modelling Parameters 51\u003c\/p\u003e \u003cp\u003e1.5.1 Diode Model 51\u003c\/p\u003e \u003cp\u003e1.5.2 MOS Transistors 52\u003c\/p\u003e \u003cp\u003e1.5.3 Advanced SPICE Models of MOS Transistors 52\u003c\/p\u003e \u003cp\u003e1.6 Passive Devices 55\u003c\/p\u003e \u003cp\u003e1.6.1 Resistors 55\u003c\/p\u003e \u003cp\u003e1.6.2 Capacitors 59\u003c\/p\u003e \u003cp\u003e1.7 Appendix 61\u003c\/p\u003e \u003cp\u003e1.7.1 Diode Exponential Relationship 61\u003c\/p\u003e \u003cp\u003e1.7.2 Diode-Diffusion Capacitance 63\u003c\/p\u003e \u003cp\u003e1.7.3 MOS Threshold Voltage and the Body Effect 65\u003c\/p\u003e \u003cp\u003e1.7.4 MOS Triode Relationship 67\u003c\/p\u003e \u003cp\u003e1.8 Key Points 69\u003c\/p\u003e \u003cp\u003e1.9 References 70\u003c\/p\u003e \u003cp\u003e1.10 Problems 70\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 2 PROCESSING AND LAYOUT 73\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 CMOS Processing 73\u003c\/p\u003e \u003cp\u003e2.1.1 The Silicon Wafer 73\u003c\/p\u003e \u003cp\u003e2.1.2 Photolithography and Well Definition 74\u003c\/p\u003e \u003cp\u003e2.1.3 Diffusion and Ion Implantation 76\u003c\/p\u003e \u003cp\u003e2.1.4 Chemical Vapor Deposition and Defining the Active Regions 78\u003c\/p\u003e \u003cp\u003e2.1.5 Transistor Isolation 78\u003c\/p\u003e \u003cp\u003e2.1.6 Gate-Oxide and Threshold-Voltage Adjustments 81\u003c\/p\u003e \u003cp\u003e2.1.7 Polysilicon Gate Formation 82\u003c\/p\u003e \u003cp\u003e2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes 82\u003c\/p\u003e \u003cp\u003e2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition 84\u003c\/p\u003e \u003cp\u003e2.1.10 Additional Processing Steps 84\u003c\/p\u003e \u003cp\u003e2.2 CMOS Layout and Design Rules 86\u003c\/p\u003e \u003cp\u003e2.2.1 Spacing Rules 86\u003c\/p\u003e \u003cp\u003e2.2.2 Planarity and Fill Requirements 94\u003c\/p\u003e \u003cp\u003e2.2.3 Antenna Rules 94\u003c\/p\u003e \u003cp\u003e2.2.4 Latch-Up 95\u003c\/p\u003e \u003cp\u003e2.3 Variability and Mismatch 96\u003c\/p\u003e \u003cp\u003e2.3.1 Systematic Variations Including Proximity Effects 96\u003c\/p\u003e \u003cp\u003e2.3.2 Process Variations 98\u003c\/p\u003e \u003cp\u003e2.3.3 Random Variations and Mismatch 99\u003c\/p\u003e \u003cp\u003e2.4 Analog Layout Considerations 103\u003c\/p\u003e \u003cp\u003e2.4.1 Transistor Layouts 103\u003c\/p\u003e \u003cp\u003e2.4.2 Capacitor Matching 104\u003c\/p\u003e \u003cp\u003e2.4.3 Resistor Layout 107\u003c\/p\u003e \u003cp\u003e2.4.4 Noise Considerations 109\u003c\/p\u003e \u003cp\u003e2.5 Key Points 112\u003c\/p\u003e \u003cp\u003e2.6 References 113\u003c\/p\u003e \u003cp\u003e2.7 Problems 114\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 3 BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS 117\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Simple CMOS Current Mirror 118\u003c\/p\u003e \u003cp\u003e3.2 Common-Source Amplifier 120\u003c\/p\u003e \u003cp\u003e3.3 Source-Follower or Common-Drain Amplifier 122\u003c\/p\u003e \u003cp\u003e3.4 Common-Gate Amplifier 124\u003c\/p\u003e \u003cp\u003e3.5 Source-Degenerated Current Mirrors 127\u003c\/p\u003e \u003cp\u003e3.6 Cascode Current Mirrors 129\u003c\/p\u003e \u003cp\u003e3.7 Cascode Gain Stage 131\u003c\/p\u003e \u003cp\u003e3.8 MOS Differential Pair and Gain Stage 135\u003c\/p\u003e \u003cp\u003e3.9 Key Points 138\u003c\/p\u003e \u003cp\u003e3.10 References 139\u003c\/p\u003e \u003cp\u003e3.11 Problems 139\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS 144\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Frequency Response of Linear Systems 144\u003c\/p\u003e \u003cp\u003e4.1.1 Magnitude and Phase Response 145\u003c\/p\u003e \u003cp\u003e4.1.2 First-Order Circuits 147\u003c\/p\u003e \u003cp\u003e4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles 154\u003c\/p\u003e \u003cp\u003e4.1.4 Bode Plots 157\u003c\/p\u003e \u003cp\u003e4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles 163\u003c\/p\u003e \u003cp\u003e4.2 Frequency Response of Elementary Transistor Circuits 164\u003c\/p\u003e \u003cp\u003e4.2.1 High-Frequency MOS Small-Signal Model 164\u003c\/p\u003e \u003cp\u003e4.2.2 Common-Source Amplifier 166\u003c\/p\u003e \u003cp\u003e4.2.3 Miller Theorem and Miller Effect 169\u003c\/p\u003e \u003cp\u003e4.2.4 Zero-Value Time-Constant Analysis 173\u003c\/p\u003e \u003cp\u003e4.2.5 Common-Source Design Examples 176\u003c\/p\u003e \u003cp\u003e4.2.6 Common-Gate Amplifier 179\u003c\/p\u003e \u003cp\u003e4.3 Cascode Gain Stage 181\u003c\/p\u003e \u003cp\u003e4.4 Source-Follower Amplifier 187\u003c\/p\u003e \u003cp\u003e4.5 Differential Pair 193\u003c\/p\u003e \u003cp\u003e4.5.1 High-Frequency T Model 193\u003c\/p\u003e \u003cp\u003e4.5.2 Symmetric Differential Amplifier 194\u003c\/p\u003e \u003cp\u003e4.5.3 Single-Ended Differential Amplifier 195\u003c\/p\u003e \u003cp\u003e4.5.4 Differential Pair with Active Load 196\u003c\/p\u003e \u003cp\u003e4.6 Key Points 197\u003c\/p\u003e \u003cp\u003e4.7 References 198\u003c\/p\u003e \u003cp\u003e4.8 Problems 198\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 5 FEEDBACK AMPLIFIERS 204\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Ideal Model of Negative Feedback 204\u003c\/p\u003e \u003cp\u003e5.1.1 Basic Definitions 204\u003c\/p\u003e \u003cp\u003e5.1.2 Gain Sensitivity 205\u003c\/p\u003e \u003cp\u003e5.1.3 Bandwidth 206\u003c\/p\u003e \u003cp\u003e5.1.4 Linearity 207\u003c\/p\u003e \u003cp\u003e5.1.5 Summary 207\u003c\/p\u003e \u003cp\u003e5.2 Dynamic Response of Feedback Amplifiers 208\u003c\/p\u003e \u003cp\u003e5.2.1 Stability Criteria 209\u003c\/p\u003e \u003cp\u003e5.2.2 Phase Margin 211\u003c\/p\u003e \u003cp\u003e5.3 First- and Second-Order Feedback Systems 213\u003c\/p\u003e \u003cp\u003e5.3.1 First-Order Feedback Systems 213\u003c\/p\u003e \u003cp\u003e5.3.2 Second-Order Feedback Systems 217\u003c\/p\u003e \u003cp\u003e5.3.3 Higher-Order Feedback Systems 220\u003c\/p\u003e \u003cp\u003e5.4 Common Feedback Amplifiers 221\u003c\/p\u003e \u003cp\u003e5.4.1 Obtaining the Loop Gain, L(s) 222\u003c\/p\u003e \u003cp\u003e5.4.2 Noninverting Amplifier 226\u003c\/p\u003e \u003cp\u003e5.4.3 Transimpedance (Inverting) Amplifiers 231\u003c\/p\u003e \u003cp\u003e5.5 Summary of Key Points 235\u003c\/p\u003e \u003cp\u003e5.6 References 236\u003c\/p\u003e \u003cp\u003e5.7 Problems 236\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 6 BASIC OPAMP DESIGN AND COMPENSATION 242\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Two-Stage CMOS Opamp 242\u003c\/p\u003e \u003cp\u003e6.1.1 Opamp Gain 243\u003c\/p\u003e \u003cp\u003e6.1.2 Frequency Response 245\u003c\/p\u003e \u003cp\u003e6.1.3 Slew Rate 249\u003c\/p\u003e \u003cp\u003e6.1.4 n-Channel or p-Channel Input Stage 252\u003c\/p\u003e \u003cp\u003e6.1.5 Systematic Offset Voltage 253\u003c\/p\u003e \u003cp\u003e6.2 Opamp Compensation 254\u003c\/p\u003e \u003cp\u003e6.2.1 Dominant-Pole Compensation and Lead Compensation 255\u003c\/p\u003e \u003cp\u003e6.2.2 Compensating the Two-Stage Opamp 256\u003c\/p\u003e \u003cp\u003e6.2.3 Making Compensation Independent of Process and Temperature 260\u003c\/p\u003e \u003cp\u003e6.3 Advanced Current Mirrors 262\u003c\/p\u003e \u003cp\u003e6.3.1 Wide-Swing Current Mirrors 262\u003c\/p\u003e \u003cp\u003e6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting 263\u003c\/p\u003e \u003cp\u003e6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance 266\u003c\/p\u003e \u003cp\u003e6.3.4 Current-Mirror Symbol 267\u003c\/p\u003e \u003cp\u003e6.4 Folded-Cascode Opamp 268\u003c\/p\u003e \u003cp\u003e6.4.1 Small-Signal Analysis 270\u003c\/p\u003e \u003cp\u003e6.4.2 Slew Rate 272\u003c\/p\u003e \u003cp\u003e6.5 Current Mirror Opamp 275\u003c\/p\u003e \u003cp\u003e6.6 Linear Settling Time Revisited 279\u003c\/p\u003e \u003cp\u003e6.7 Fully Differential Opamps 281\u003c\/p\u003e \u003cp\u003e6.7.1 Fully Differential Folded-Cascode Opamp 283\u003c\/p\u003e \u003cp\u003e6.7.2 Alternative Fully Differential Opamps 284\u003c\/p\u003e \u003cp\u003e6.7.3 Low Supply Voltage Opamps 286\u003c\/p\u003e \u003cp\u003e6.8 Common-Mode Feedback Circuits 288\u003c\/p\u003e \u003cp\u003e6.9 Summary of Key Points 292\u003c\/p\u003e \u003cp\u003e6.10 References 293\u003c\/p\u003e \u003cp\u003e6.11 Problems 294\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 7 BIASING, REFERENCES, AND REGULATORS 302\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Analog Integrated Circuit Biasing 302\u003c\/p\u003e \u003cp\u003e7.1.1 Bias Circuits 303\u003c\/p\u003e \u003cp\u003e7.1.2 Reference Circuits 305\u003c\/p\u003e \u003cp\u003e7.1.3 Regulator Circuits 306\u003c\/p\u003e \u003cp\u003e7.2 Establishing Constant Transconductance 307\u003c\/p\u003e \u003cp\u003e7.2.1 Basic Constant-Transconductance Circuit 307\u003c\/p\u003e \u003cp\u003e7.2.2 Improved Constant-Transconductance Circuits 309\u003c\/p\u003e \u003cp\u003e7.3 Establishing Constant Voltages and Currents 310\u003c\/p\u003e \u003cp\u003e7.3.1 Bandgap Voltage Reference Basics 310\u003c\/p\u003e \u003cp\u003e7.3.2 Circuits for Bandgap References 314\u003c\/p\u003e \u003cp\u003e7.3.3 Low-Voltage Bandgap Reference 319\u003c\/p\u003e \u003cp\u003e7.3.4 Current Reference 320\u003c\/p\u003e \u003cp\u003e7.4 Voltage Regulation 321\u003c\/p\u003e \u003cp\u003e7.4.1 Regulator Specifications 321\u003c\/p\u003e \u003cp\u003e7.4.2 Feedback Analysis 322\u003c\/p\u003e \u003cp\u003e7.4.3 Low Dropout Regulators 324\u003c\/p\u003e \u003cp\u003e7.5 Summary of Key Points 327\u003c\/p\u003e \u003cp\u003e7.6 References 327\u003c\/p\u003e \u003cp\u003e7.7 Problems 328\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 8 BIPOLAR DEVICES AND CIRCUITS 331\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Bipolar-Junction Transistors 331\u003c\/p\u003e \u003cp\u003e8.1.1 Basic Operation 331\u003c\/p\u003e \u003cp\u003e8.1.2 Analog Figures of Merit 341\u003c\/p\u003e \u003cp\u003e8.2 Bipolar Device Model Summary 344\u003c\/p\u003e \u003cp\u003e8.3 SPICE Modeling 345\u003c\/p\u003e \u003cp\u003e8.4 Bipolar and BICMOS Processing 346\u003c\/p\u003e \u003cp\u003e8.4.1 Bipolar Processing 346\u003c\/p\u003e \u003cp\u003e8.4.2 Modern SiGe BiCMOS HBT Processing 347\u003c\/p\u003e \u003cp\u003e8.4.3 Mismatch in Bipolar Devices 348\u003c\/p\u003e \u003cp\u003e8.5 Bipolar Current Mirrors and Gain Stages 349\u003c\/p\u003e \u003cp\u003e8.5.1 Current Mirrors 349\u003c\/p\u003e \u003cp\u003e8.5.2 Emitter Follower 350\u003c\/p\u003e \u003cp\u003e8.5.3 Bipolar Differential Pair 353\u003c\/p\u003e \u003cp\u003e8.6 Appendix 356\u003c\/p\u003e \u003cp\u003e8.6.1 Bipolar Transistor Exponential Relationship 356\u003c\/p\u003e \u003cp\u003e8.6.2 Base Charge Storage of an Active BJT 359\u003c\/p\u003e \u003cp\u003e8.7 Summary of Key Points 359\u003c\/p\u003e \u003cp\u003e8.8 References 360\u003c\/p\u003e \u003cp\u003e8.9 Problems 360\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING 363\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Time-Domain Analysis 363\u003c\/p\u003e \u003cp\u003e9.1.1 Root Mean Square (rms) Value 364\u003c\/p\u003e \u003cp\u003e9.1.2 SNR 365\u003c\/p\u003e \u003cp\u003e9.1.3 Units of dBm 365\u003c\/p\u003e \u003cp\u003e9.1.4 Noise Summation 366\u003c\/p\u003e \u003cp\u003e9.2 Frequency-Domain Analysis 367\u003c\/p\u003e \u003cp\u003e9.2.1 Noise Spectral Density 367\u003c\/p\u003e \u003cp\u003e9.2.2 White Noise 369\u003c\/p\u003e \u003cp\u003e9.2.3 1\/f, or Flicker, Noise 370\u003c\/p\u003e \u003cp\u003e9.2.4 Filtered Noise 371\u003c\/p\u003e \u003cp\u003e9.2.5 Noise Bandwidth 373\u003c\/p\u003e \u003cp\u003e9.2.6 Piecewise Integration of Noise 375\u003c\/p\u003e \u003cp\u003e9.2.7 1\/f Noise Tangent Principle 377\u003c\/p\u003e \u003cp\u003e9.3 Noise Models for Circuit Elements 377\u003c\/p\u003e \u003cp\u003e9.3.1 Resistors 378\u003c\/p\u003e \u003cp\u003e9.3.2 Diodes 378\u003c\/p\u003e \u003cp\u003e9.3.3 Bipolar Transistors 380\u003c\/p\u003e \u003cp\u003e9.3.4 MOSFETS 380\u003c\/p\u003e \u003cp\u003e9.3.5 Opamps 382\u003c\/p\u003e \u003cp\u003e9.3.6 Capacitors and Inductors 382\u003c\/p\u003e \u003cp\u003e9.3.7 Sampled Signal Noise 384\u003c\/p\u003e \u003cp\u003e9.3.8 Input-Referred Noise 384\u003c\/p\u003e \u003cp\u003e9.4 Noise Analysis Examples 387\u003c\/p\u003e \u003cp\u003e9.4.1 Opamp Example 387\u003c\/p\u003e \u003cp\u003e9.4.2 Bipolar Common-Emitter Example 390\u003c\/p\u003e \u003cp\u003e9.4.3 CMOS Differential Pair Example 392\u003c\/p\u003e \u003cp\u003e9.4.4 Fiber-Optic Transimpedance Amplifier Example 395\u003c\/p\u003e \u003cp\u003e9.5 Dynamic Range Performance 397\u003c\/p\u003e \u003cp\u003e9.5.1 Total Harmonic Distortion (THD) 398\u003c\/p\u003e \u003cp\u003e9.5.2 Third-Order Intercept Point (IP3) 400\u003c\/p\u003e \u003cp\u003e9.5.3 Spurious-Free Dynamic Range (SFDR) 402\u003c\/p\u003e \u003cp\u003e9.5.4 Signal-to-Noise and Distortion Ratio (SNDR) 404\u003c\/p\u003e \u003cp\u003e9.6 Key Points 405\u003c\/p\u003e \u003cp\u003e9.7 References 406\u003c\/p\u003e \u003cp\u003e9.8 Problems 406\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 10 COMPARATORS 413\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Comparator Specifications 413\u003c\/p\u003e \u003cp\u003e10.1.1 Input Offset and Noise 413\u003c\/p\u003e \u003cp\u003e10.1.2 Hysteresis 414\u003c\/p\u003e \u003cp\u003e10.2 Using an Opamp for a Comparator 415\u003c\/p\u003e \u003cp\u003e10.2.1 Input-Offset Voltage Errors 417\u003c\/p\u003e \u003cp\u003e10.3 Charge-Injection Errors 418\u003c\/p\u003e \u003cp\u003e10.3.1 Making Charge-Injection Signal Independent 421\u003c\/p\u003e \u003cp\u003e10.3.2 Minimizing Errors Due to Charge-Injection 421\u003c\/p\u003e \u003cp\u003e10.3.3 Speed of Multi-Stage Comparators 424\u003c\/p\u003e \u003cp\u003e10.4 Latched Comparators 426\u003c\/p\u003e \u003cp\u003e10.4.1 Latch-Mode Time Constant 428\u003c\/p\u003e \u003cp\u003e10.4.2 Latch Offset 430\u003c\/p\u003e \u003cp\u003e10.5 Examples of CMOS and BiCMOS Comparators 432\u003c\/p\u003e \u003cp\u003e10.5.1 Input-Transistor Charge Trapping 435\u003c\/p\u003e \u003cp\u003e10.6 Examples of Bipolar Comparators 437\u003c\/p\u003e \u003cp\u003e10.7 Key Points 439\u003c\/p\u003e \u003cp\u003e10.8 References 440\u003c\/p\u003e \u003cp\u003e10.9 Problems 441\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 11 SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS 444\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Performance of Sample-and-Hold Circuits 444\u003c\/p\u003e \u003cp\u003e11.1.1 Testing Sample-and-Holds 445\u003c\/p\u003e \u003cp\u003e11.2 MOS Sample-and-Hold Basics 446\u003c\/p\u003e \u003cp\u003e11.3 Examples of CMOS S\/H Circuits 452\u003c\/p\u003e \u003cp\u003e11.4 Bipolar and BiCMOS Sample-and-Holds 456\u003c\/p\u003e \u003cp\u003e11.5 Translinear Gain Cell 460\u003c\/p\u003e \u003cp\u003e11.6 Translinear Multiplier 462\u003c\/p\u003e \u003cp\u003e11.7 Key Points 464\u003c\/p\u003e \u003cp\u003e11.8 References 465\u003c\/p\u003e \u003cp\u003e11.9 Problems 466\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 12 CONTINUOUS-TIME FILTERS 469\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction to Continuous-Time Filters 469\u003c\/p\u003e \u003cp\u003e12.1.1 First-Order Filters 470\u003c\/p\u003e \u003cp\u003e12.1.2 Second-Order Filters 470\u003c\/p\u003e \u003cp\u003e12.2 Introduction to Gm-C Filters 471\u003c\/p\u003e \u003cp\u003e12.2.1 Integrators and Summers 472\u003c\/p\u003e \u003cp\u003e12.2.2 Fully Differential Integrators 473\u003c\/p\u003e \u003cp\u003e12.2.3 First-Order Filter 475\u003c\/p\u003e \u003cp\u003e12.2.4 Biquad Filter 477\u003c\/p\u003e \u003cp\u003e12.3 Transconductors Using Fixed Resistors 478\u003c\/p\u003e \u003cp\u003e12.4 CMOS Transconductors Using Triode Transistors 483\u003c\/p\u003e \u003cp\u003e12.4.1 Transconductors Using a Fixed-Bias Triode Transistor 484\u003c\/p\u003e \u003cp\u003e12.4.2 Transconductors Using Varying Bias-Triode Transistors 486\u003c\/p\u003e \u003cp\u003e12.4.3 Transconductors Using Constant Drain-Source Voltages 490\u003c\/p\u003e \u003cp\u003e12.5 CMOS Transconductors Using Active Transistors 492\u003c\/p\u003e \u003cp\u003e12.5.1 CMOS Pair 493\u003c\/p\u003e \u003cp\u003e12.5.2 Constant Sum of Gate-Source Voltages 494\u003c\/p\u003e \u003cp\u003e12.5.3 Source-Connected Differential Pair 495\u003c\/p\u003e \u003cp\u003e12.5.4 Inverter-Based 495\u003c\/p\u003e \u003cp\u003e12.5.5 Differential-Pair with Floating Voltage Sources 496\u003c\/p\u003e \u003cp\u003e12.5.6 Bias-Offset Cross-Coupled Differential Pairs 499\u003c\/p\u003e \u003cp\u003e12.6 Bipolar Transconductors 499\u003c\/p\u003e \u003cp\u003e12.6.1 Gain-Cell Transconductors 500\u003c\/p\u003e \u003cp\u003e12.6.2 Transconductors Using Multiple Differential Pairs 502\u003c\/p\u003e \u003cp\u003e12.7 BiCMOS Transconductors 506\u003c\/p\u003e \u003cp\u003e12.7.1 Tunable MOS in Triode 506\u003c\/p\u003e \u003cp\u003e12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier 507\u003c\/p\u003e \u003cp\u003e12.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier 508\u003c\/p\u003e \u003cp\u003e12.8 Active RC and MOSFET-C Filters 509\u003c\/p\u003e \u003cp\u003e12.8.1 Active RC Filters 510\u003c\/p\u003e \u003cp\u003e12.8.2 MOSFET-C Two-Transistor Integrators 512\u003c\/p\u003e \u003cp\u003e12.8.3 Four-Transistor Integrators 515\u003c\/p\u003e \u003cp\u003e12.8.4 R-MOSFET-C Filters 516\u003c\/p\u003e \u003cp\u003e12.9 Tuning Circuitry 517\u003c\/p\u003e \u003cp\u003e12.9.1 Tuning Overview 517\u003c\/p\u003e \u003cp\u003e12.9.2 Constant Transconductance 519\u003c\/p\u003e \u003cp\u003e12.9.3 Frequency Tuning 520\u003c\/p\u003e \u003cp\u003e12.9.4 Q-Factor Tuning 522\u003c\/p\u003e \u003cp\u003e12.9.5 Tuning Methods Based on Adaptive Filtering 523\u003c\/p\u003e \u003cp\u003e12.10 Introduction to Complex Filters 525\u003c\/p\u003e \u003cp\u003e12.10.1 Complex Signal Processing 525\u003c\/p\u003e \u003cp\u003e12.10.2 Complex Operations 526\u003c\/p\u003e \u003cp\u003e12.10.3 Complex Filters 527\u003c\/p\u003e \u003cp\u003e12.10.4 Frequency-Translated Analog Filters 528\u003c\/p\u003e \u003cp\u003e12.11 Key Points 531\u003c\/p\u003e \u003cp\u003e12.12 References 532\u003c\/p\u003e \u003cp\u003e12.13 Problems 534\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 13 DISCRETE-TIME SIGNALS 537\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Overview of Some Signal Spectra 537\u003c\/p\u003e \u003cp\u003e13.2 Laplace Transforms of Discrete-Time Signals 537\u003c\/p\u003e \u003cp\u003e13.2.1 Spectra of Discrete-Time Signals 540\u003c\/p\u003e \u003cp\u003e13.3 z-Transform 541\u003c\/p\u003e \u003cp\u003e13.4 Downsampling and Upsampling 543\u003c\/p\u003e \u003cp\u003e13.5 Discrete-Time Filters 545\u003c\/p\u003e \u003cp\u003e13.5.1 Frequency Response of Discrete-Time Filters 545\u003c\/p\u003e \u003cp\u003e13.5.2 Stability of Discrete-Time Filters 548\u003c\/p\u003e \u003cp\u003e13.5.3 IIR and FIR Filters 550\u003c\/p\u003e \u003cp\u003e13.5.4 Bilinear Transform 550\u003c\/p\u003e \u003cp\u003e13.6 Sample-and-Hold Response 552\u003c\/p\u003e \u003cp\u003e13.7 Key Points 554\u003c\/p\u003e \u003cp\u003e13.8 References 555\u003c\/p\u003e \u003cp\u003e13.9 Problems 555\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 14 SWITCHED-CAPACITOR CIRCUITS 557\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Basic Building Blocks 557\u003c\/p\u003e \u003cp\u003e14.1.1 Opamps 557\u003c\/p\u003e \u003cp\u003e14.1.2 Capacitors 558\u003c\/p\u003e \u003cp\u003e14.1.3 Switches 558\u003c\/p\u003e \u003cp\u003e14.1.4 Nonoverlapping Clocks 559\u003c\/p\u003e \u003cp\u003e14.2 Basic Operation and Analysis 560\u003c\/p\u003e \u003cp\u003e14.2.1 Resistor Equivalence of a Switched Capacitor 560\u003c\/p\u003e \u003cp\u003e14.2.2 Parasitic-Sensitive Integrator 563\u003c\/p\u003e \u003cp\u003e14.2.3 Parasitic-Insensitive Integrators 565\u003c\/p\u003e \u003cp\u003e14.2.4 Signal-Flow-Graph Analysis 569\u003c\/p\u003e \u003cp\u003e14.3 Noise in Switched-Capacitor Circuits 570\u003c\/p\u003e \u003cp\u003e14.4 First-Order Filters 572\u003c\/p\u003e \u003cp\u003e14.4.1 Switch Sharing 575\u003c\/p\u003e \u003cp\u003e14.4.2 Fully Differential Filters 575\u003c\/p\u003e \u003cp\u003e14.5 Biquad Filters 577\u003c\/p\u003e \u003cp\u003e14.5.1 Low-Q Biquad Filter 577\u003c\/p\u003e \u003cp\u003e14.5.2 High-Q Biquad Filter 581\u003c\/p\u003e \u003cp\u003e14.6 Charge Injection 585\u003c\/p\u003e \u003cp\u003e14.7 Switched-Capacitor Gain Circuits 588\u003c\/p\u003e \u003cp\u003e14.7.1 Parallel Resistor-Capacitor Circuit 588\u003c\/p\u003e \u003cp\u003e14.7.2 Resettable Gain Circuit 588\u003c\/p\u003e \u003cp\u003e14.7.3 Capacitive-Reset Gain Circuit 591\u003c\/p\u003e \u003cp\u003e14.8 Correlated Double-Sampling Techniques 593\u003c\/p\u003e \u003cp\u003e14.9 Other Switched-Capacitor Circuits 594\u003c\/p\u003e \u003cp\u003e14.9.1 Amplitude Modulator 594\u003c\/p\u003e \u003cp\u003e14.9.2 Full-Wave Rectifier 595\u003c\/p\u003e \u003cp\u003e14.9.3 Peak Detectors 596\u003c\/p\u003e \u003cp\u003e14.9.4 Voltage-Controlled Oscillator 596\u003c\/p\u003e \u003cp\u003e14.9.5 Sinusoidal Oscillator 598\u003c\/p\u003e \u003cp\u003e14.10 Key Points 600\u003c\/p\u003e \u003cp\u003e14.11 References 601\u003c\/p\u003e \u003cp\u003e14.12 Problems 602\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 15 DATA CONVERTER FUNDAMENTALS 606\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Ideal D\/A Converter 606\u003c\/p\u003e \u003cp\u003e15.2 Ideal A\/D Converter 608\u003c\/p\u003e \u003cp\u003e15.3 Quantization Noise 609\u003c\/p\u003e \u003cp\u003e15.3.1 Deterministic Approach 609\u003c\/p\u003e \u003cp\u003e15.3.2 Stochastic Approach 610\u003c\/p\u003e \u003cp\u003e15.4 Signed Codes 612\u003c\/p\u003e \u003cp\u003e15.5 Performance Limitations 614\u003c\/p\u003e \u003cp\u003e15.5.1 Resolution 614\u003c\/p\u003e \u003cp\u003e15.5.2 Offset and Gain Error 615\u003c\/p\u003e \u003cp\u003e15.5.3 Accuracy and Linearity 615\u003c\/p\u003e \u003cp\u003e15.6 Key Points 620\u003c\/p\u003e \u003cp\u003e15.7 References 620\u003c\/p\u003e \u003cp\u003e15.8 Problems 620\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 16 NYQUIST-RATE D\/A CONVERTERS 623\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Decoder-Based Converters 623\u003c\/p\u003e \u003cp\u003e16.1.1 Resistor-String Converters 623\u003c\/p\u003e \u003cp\u003e16.1.2 Folded Resistor-String Converters 625\u003c\/p\u003e \u003cp\u003e16.1.3 Multiple Resistor-String Converters 626\u003c\/p\u003e \u003cp\u003e16.1.4 Signed Outputs 628\u003c\/p\u003e \u003cp\u003e16.2 Binary-Scaled Converters 629\u003c\/p\u003e \u003cp\u003e16.2.1 Binary-Weighted Resistor Converters 629\u003c\/p\u003e \u003cp\u003e16.2.2 Reduced-Resistance-Ratio Ladders 630\u003c\/p\u003e \u003cp\u003e16.2.3 R-2R-Based Converters 631\u003c\/p\u003e \u003cp\u003e16.2.4 Charge-Redistribution Switched-Capacitor Converters 632\u003c\/p\u003e \u003cp\u003e16.2.5 Current-Mode Converters 633\u003c\/p\u003e \u003cp\u003e16.2.6 Glitches 633\u003c\/p\u003e \u003cp\u003e16.3 Thermometer-Code Converters 634\u003c\/p\u003e \u003cp\u003e16.3.1 Thermometer-Code Current-Mode D\/A Converters 636\u003c\/p\u003e \u003cp\u003e16.3.2 Single-Supply Positive-Output Converters 637\u003c\/p\u003e \u003cp\u003e16.3.3 Dynamically Matched Current Sources 638\u003c\/p\u003e \u003cp\u003e16.4 Hybrid Converters 640\u003c\/p\u003e \u003cp\u003e16.4.1 Resistor-Capacitor Hybrid Converters 640\u003c\/p\u003e \u003cp\u003e16.4.2 Segmented Converters 640\u003c\/p\u003e \u003cp\u003e16.5 Key Points 642\u003c\/p\u003e \u003cp\u003e16.6 References 643\u003c\/p\u003e \u003cp\u003e16.7 Problems 643\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 17 NYQUIST-RATE A\/D CONVERTERS 646\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Integrating Converters 646\u003c\/p\u003e \u003cp\u003e17.2 Successive-Approximation Converters 650\u003c\/p\u003e \u003cp\u003e17.2.1 D\/A-Based Successive Approximation 652\u003c\/p\u003e \u003cp\u003e17.2.2 Charge-Redistribution A\/D 653\u003c\/p\u003e \u003cp\u003e17.2.3 Resistor-Capacitor Hybrid 658\u003c\/p\u003e \u003cp\u003e17.2.4 Speed Estimate for Charge-Redistribution Converters 659\u003c\/p\u003e \u003cp\u003e17.2.5 Error Correction in Successive-Approximation Converters 660\u003c\/p\u003e \u003cp\u003e17.2.6 Multi-Bit Successive-Approximation 662\u003c\/p\u003e \u003cp\u003e17.3 Algorithmic (or Cyclic) A\/D Converter 662\u003c\/p\u003e \u003cp\u003e17.3.1 Ratio-Independent Algorithmic Converter 663\u003c\/p\u003e \u003cp\u003e17.4 Pipelined A\/D Converters 667\u003c\/p\u003e \u003cp\u003e17.4.1 One-Bit-Per-Stage Pipelined Converter 667\u003c\/p\u003e \u003cp\u003e17.4.2 1.5 Bit Per Stage Pipelined Converter 670\u003c\/p\u003e \u003cp\u003e17.4.3 Pipelined Converter Circuits 673\u003c\/p\u003e \u003cp\u003e17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters 673\u003c\/p\u003e \u003cp\u003e17.5 Flash Converters 674\u003c\/p\u003e \u003cp\u003e17.5.1 Issues in Designing Flash A\/D Converters 675\u003c\/p\u003e \u003cp\u003e17.6 Two-Step A\/D Converters 678\u003c\/p\u003e \u003cp\u003e17.6.1 Two-Step Converter with Digital Error Correction 679\u003c\/p\u003e \u003cp\u003e17.7 Interpolating A\/D Converters 681\u003c\/p\u003e \u003cp\u003e17.8 Folding A\/D Converters 684\u003c\/p\u003e \u003cp\u003e17.9 Time-Interleaved A\/D Converters 687\u003c\/p\u003e \u003cp\u003e17.10 Key Points 690\u003c\/p\u003e \u003cp\u003e17.11 References 691\u003c\/p\u003e \u003cp\u003e17.12 Problems 692\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 18 OVERSAMPLING CONVERTERS 696\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Oversampling without Noise Shaping 696\u003c\/p\u003e \u003cp\u003e18.1.1 Quantization Noise Modelling 697\u003c\/p\u003e \u003cp\u003e18.1.2 White Noise Assumption 697\u003c\/p\u003e \u003cp\u003e18.1.3 Oversampling Advantage 698\u003c\/p\u003e \u003cp\u003e18.1.4 The Advantage of 1-Bit D\/A Converters 700\u003c\/p\u003e \u003cp\u003e18.2 Oversampling with Noise Shaping 701\u003c\/p\u003e \u003cp\u003e18.2.1 Noise-Shaped Delta-Sigma Modulator 702\u003c\/p\u003e \u003cp\u003e18.2.2 First-Order Noise Shaping 703\u003c\/p\u003e \u003cp\u003e18.2.3 Switched-Capacitor Realization of a First-Order A\/D Converter 705\u003c\/p\u003e \u003cp\u003e18.2.4 Second-Order Noise Shaping 705\u003c\/p\u003e \u003cp\u003e18.2.5 Noise Transfer-Function Curves 707\u003c\/p\u003e \u003cp\u003e18.2.6 Quantization Noise Power of 1-Bit Modulators 708\u003c\/p\u003e \u003cp\u003e18.2.7 Error-Feedback Structure 708\u003c\/p\u003e \u003cp\u003e18.3 System Architectures 710\u003c\/p\u003e \u003cp\u003e18.3.1 System Architecture of Delta-Sigma A\/D Converters 710\u003c\/p\u003e \u003cp\u003e18.3.2 System Architecture of Delta-Sigma D\/A Converters 712\u003c\/p\u003e \u003cp\u003e18.4 Digital Decimation Filters 713\u003c\/p\u003e \u003cp\u003e18.4.1 Multi-Stage 714\u003c\/p\u003e \u003cp\u003e18.4.2 Single Stage 716\u003c\/p\u003e \u003cp\u003e18.5 Higher-Order Modulators 717\u003c\/p\u003e \u003cp\u003e18.5.1 Interpolative Architecture 717\u003c\/p\u003e \u003cp\u003e18.5.2 Multi-Stage Noise Shaping (MASH) Architecture 718\u003c\/p\u003e \u003cp\u003e18.6 Bandpass Oversampling Converters 720\u003c\/p\u003e \u003cp\u003e18.7 Practical Considerations 721\u003c\/p\u003e \u003cp\u003e18.7.1 Stability 721\u003c\/p\u003e \u003cp\u003e18.7.2 Linearity of Two-Level Converters 722\u003c\/p\u003e \u003cp\u003e18.7.3 Idle Tones 724\u003c\/p\u003e \u003cp\u003e18.7.4 Dithering 725\u003c\/p\u003e \u003cp\u003e18.7.5 Opamp Gain 725\u003c\/p\u003e \u003cp\u003e18.8 Multi-Bit Oversampling Converters 726\u003c\/p\u003e \u003cp\u003e18.8.1 Dynamic Element Matching 726\u003c\/p\u003e \u003cp\u003e18.8.2 Dynamically Matched Current Source D\/A Converters 727\u003c\/p\u003e \u003cp\u003e18.8.3 Digital Calibration A\/D Converter 727\u003c\/p\u003e \u003cp\u003e18.8.4 A\/D with Both Multi-Bit and Single-Bit Feedback 728\u003c\/p\u003e \u003cp\u003e18.9 Third-Order A\/D Design Example 729\u003c\/p\u003e \u003cp\u003e18.10 Key Points 731\u003c\/p\u003e \u003cp\u003e18.11 References 733\u003c\/p\u003e \u003cp\u003e18.12 Problems 734\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 19 PHASE-LOCKED LOOPS 737\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Basic Phase-Locked Loop Architecture 737\u003c\/p\u003e \u003cp\u003e19.1.1 Voltage-Controlled Oscillator 738\u003c\/p\u003e \u003cp\u003e19.1.2 Divider 739\u003c\/p\u003e \u003cp\u003e19.1.3 Phase Detector 740\u003c\/p\u003e \u003cp\u003e19.1.4 Loop Filer 745\u003c\/p\u003e \u003cp\u003e19.1.5 The PLL in Lock 746\u003c\/p\u003e \u003cp\u003e19.2 Linearized Small-Signal Analysis 747\u003c\/p\u003e \u003cp\u003e19.2.1 Second-Order PLL Model 748\u003c\/p\u003e \u003cp\u003e19.2.2 Limitations of the Second-Order Small-Signal Model 750\u003c\/p\u003e \u003cp\u003e19.2.3 PLL Design Example 752\u003c\/p\u003e \u003cp\u003e19.3 Jitter and Phase Noise 754\u003c\/p\u003e \u003cp\u003e19.3.1 Period Jitter 758\u003c\/p\u003e \u003cp\u003e19.3.2 P-Cycle Jitter 758\u003c\/p\u003e \u003cp\u003e19.3.3 Adjacent Period Jitter 759\u003c\/p\u003e \u003cp\u003e19.3.4 Other Spectral Representations of Jitter 760\u003c\/p\u003e \u003cp\u003e19.3.5 Probability Density Function of Jitter 761\u003c\/p\u003e \u003cp\u003e19.4 Electronic Oscillators 763\u003c\/p\u003e \u003cp\u003e19.4.1 Ring Oscillators 764\u003c\/p\u003e \u003cp\u003e19.4.2 LC Oscillators 768\u003c\/p\u003e \u003cp\u003e19.4.3 Phase Noise of Oscillators 770\u003c\/p\u003e \u003cp\u003e19.5 Jitter and Phase Noise in PLLS 774\u003c\/p\u003e \u003cp\u003e19.5.1 Input Phase Noise and Divider Phase Noise 775\u003c\/p\u003e \u003cp\u003e19.5.2 VCO Phase Noise 775\u003c\/p\u003e \u003cp\u003e19.5.3 Loop Filter Noise 776\u003c\/p\u003e \u003cp\u003e19.6 Key Points 779\u003c\/p\u003e \u003cp\u003e19.7 References 779\u003c\/p\u003e \u003cp\u003e19.8 Problems 780\u003c\/p\u003e \u003cp\u003eINDEX 783\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley","offers":[{"title":"Brand New","offer_id":52463039676696,"sku":"9781118092330","price":43.79,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9781118092330.jpg?v=1785546463","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/analog-integrated-circuit-design-international-student-version-paperback-softback-9781118092330","provider":"Freshly Printed Books","version":"1.0","type":"link"}