{"product_id":"advanced-semiconductor-memories-architectures-designs-and-applications-hardback-9780471208136","title":"Advanced Semiconductor Memories; Architectures, Designs, and Applications (Hardback) 9780471208136","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eAdvanced Semiconductor Memories\u003c\/font\u003e\u003cbr\u003e\r\n\u003cfont size=\"5\"\u003eArchitectures, Designs, and Applications\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\u003cp\u003e\u003cfont size=\"4\"\u003eAshok K. Sharma (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471208136, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 29 October 2002\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e672 pages\u003cbr\u003e23.6 x 16 x 4.3 cm, 1.134 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003e* Ein idealer Ergänzungsband zum Vorgängertitel \"Semiconductor Memories: Technologies, Testing, and Reliability\" vom gleichen Autor.\u003cbr\u003e * \"Advanced Semiconductor Memories\" ist ein nützlicher Ratgeber für alle, die sich für den Einsatz hoch entwickelter Speicher-Konfigurationen interessieren.\u003cbr\u003e * Halbleiter-Speichermodule gehören zu den wichtigsten mikroelektronischen Bausteinen. Mit DRAMs (Dynamic Random Access Memory) werden die höchsten Umsatzerlöse bei den Halbleiterprodukten erzielt.\u003cbr\u003e * DRAMs sind die Technologietreiber für die Massenproduktion einer neuen Generation von Halbleiterprodukten, die ausser im PC-Bereich, immer mehr in den Bereichen Automobilbau, Luftfahrt, Militär und Raumfahrt sowie im Telekommunikations- und drahtlosen Bereich eingesetzt werden.\u003cbr\u003e * In den letzten Jahren hat sich eine neue Generation von hochdichten und Hochleistungs- Speicherarchitekturen herausgebildet, wie z.B. Embedded Memory (chipinterner Speicher) und Flash Memory (Blitzspeicher) für Massenspeicher mit einer breiten Palette von Einsatzgebieten.\u003cbr\u003e * \"Advanced Semiconductor Memories\" behandelt alle wichtigen Aspekte hoch entwickelter Halbleiterspeicherelemente und -technologien; darunter auch die neuesten SRAM-Entwicklungen.\u003cbr\u003e * Ein unentbehrlicher Leitfaden für Ingenieure.\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003ePREFACE xix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1. Semiconductor Memories Overview 1\u003c\/p\u003e \u003cp\u003e1.2. Advanced Semiconductor Memory Developments 8\u003c\/p\u003e \u003cp\u003e1.3. Future Memory Directions 16\u003c\/p\u003e \u003cp\u003eReferences 18\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 STATIC RANDOM ACCESS MEMORY TECHNOLOGIES 19\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1. Basic SRAM Architecture and Cell Structures 19\u003c\/p\u003e \u003cp\u003e2.1.1. SRAM Performance and Timing Specifications 21\u003c\/p\u003e \u003cp\u003e2.1.2. SRAM ReadWrite Operations 23\u003c\/p\u003e \u003cp\u003e2.2. SRAM Selection Considerations 26\u003c\/p\u003e \u003cp\u003e2.3. High Performance SRAMs 33\u003c\/p\u003e \u003cp\u003e2.3.1. Synchronous SRAMs Flow-Through 41\u003c\/p\u003e \u003cp\u003e2.3.2. Zero Bus Turnaround SRAMs 43\u003c\/p\u003e \u003cp\u003e2.3.3. Quad Data Rate SRAM 44\u003c\/p\u003e \u003cp\u003e2.3.4. Double Data Rate SRAM 50\u003c\/p\u003e \u003cp\u003e2.3.5. No-Turnaround Random Access Memory 51\u003c\/p\u003e \u003cp\u003e2.4. Advanced SRAM Architectures 55\u003c\/p\u003e \u003cp\u003e2.5. Low-Voltage SRAMs 61\u003c\/p\u003e \u003cp\u003e2.6. BiCMOS Technology SRAMs 75\u003c\/p\u003e \u003cp\u003e2.7. SOI SRAMs 79\u003c\/p\u003e \u003cp\u003e2.8. Specialty SRAMs 91\u003c\/p\u003e \u003cp\u003e2.8.1. Multiport RAMs 92\u003c\/p\u003e \u003cp\u003e2.8.1.1. Dual-Port RAMs 92\u003c\/p\u003e \u003cp\u003e2.8.1.2. Quadport™ RAMs 101\u003c\/p\u003e \u003cp\u003e2.8.2. First-In-First-Out (FIFO) Memories 103\u003c\/p\u003e \u003cp\u003e2.8.3. Content Addressable Memories (CAMs) 111\u003c\/p\u003e \u003cp\u003e2.8.3.1. Advanced Content Addressable Memories (Examples) 116\u003c\/p\u003e \u003cp\u003eReferences 122\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 HIGH-PERFORMANCE DYNAMIC RANDOM ACCESS MEMORIES 129\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1. DRAM Technology Evolution and Trends 129\u003c\/p\u003e \u003cp\u003e3.2. DRAM Timing Specifications and Operations 133\u003c\/p\u003e \u003cp\u003e3.2.1. General Timing Specifications 133\u003c\/p\u003e \u003cp\u003e3.2.2. Memory Read Operation 135\u003c\/p\u003e \u003cp\u003e3.2.3. Memory Write Operation 138\u003c\/p\u003e \u003cp\u003e3.2.4. Read-Modify-Write Operation 140\u003c\/p\u003e \u003cp\u003e3.2.5. DRAM Refresh Operation 141\u003c\/p\u003e \u003cp\u003e3.3. Extended-Data-Out DRAMS 145\u003c\/p\u003e \u003cp\u003e3.3.1. EDO DRAM (Example) 145\u003c\/p\u003e \u003cp\u003e3.4. Enhanced DRAM (EDRAM) 146\u003c\/p\u003e \u003cp\u003e3.5. Synchronous DRAMGRAM Architectures 150\u003c\/p\u003e \u003cp\u003e3.5.1. SDR SDRAMSGRAM 150\u003c\/p\u003e \u003cp\u003e3.5.2. DDR SDRAMSGRAM Features 151\u003c\/p\u003e \u003cp\u003e3.5.3. Synchronous DRAM 256Mb (Example) 154\u003c\/p\u003e \u003cp\u003e3.5.3.1. Initialization 154\u003c\/p\u003e \u003cp\u003e3.5.3.2. Register Definition 155\u003c\/p\u003e \u003cp\u003e3.5.3.3. Commands 157\u003c\/p\u003e \u003cp\u003e3.5.3.4. SDRAM Operations 159\u003c\/p\u003e \u003cp\u003e3.6. Enhanced Synchronous DRAM (ESDRAM) 163\u003c\/p\u003e \u003cp\u003e3.7. Cache DRAM (CDRAM) 166\u003c\/p\u003e \u003cp\u003e3.8. Virtual Channel Memory (VCM) DRAMs 172\u003c\/p\u003e \u003cp\u003e3.9. Advaned DRAM Technology Perspectives 175\u003c\/p\u003e \u003cp\u003e3.9.1. Memory Capacitor Cell Improvements 179\u003c\/p\u003e \u003cp\u003e3.9.2. 64-Mb DRAMs 188\u003c\/p\u003e \u003cp\u003e3.9.3. 256-Mb DRAMs 195\u003c\/p\u003e \u003cp\u003e3.10. Gigabit DRAM Scaling Issues and Architectures 200\u003c\/p\u003e \u003cp\u003e3.11. Multilevel Storage DRAMs 217\u003c\/p\u003e \u003cp\u003e3.12. SOI DRAMs 221\u003c\/p\u003e \u003cp\u003eReferences 231\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 APPLICATION-SPECIFIC DRAM ARCHITECTURES AND DESIGNS 237\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1. Video RAMs (VRAMs) 241\u003c\/p\u003e \u003cp\u003e4.2. Synchronous Graphic RAMs (SGRAMs) 244\u003c\/p\u003e \u003cp\u003e4.2.1. 64-Mb DDR SGRAM 246\u003c\/p\u003e \u003cp\u003e4.2.2. 256-Mb DDR Fast Cycle RAM 253\u003c\/p\u003e \u003cp\u003e4.3. Rambus Technology Overview 257\u003c\/p\u003e \u003cp\u003e4.3.1. Direct RDRAM Technologies and Architectures 264\u003c\/p\u003e \u003cp\u003e4.3.2. Direct Rambus Memory System-Based Designs 272\u003c\/p\u003e \u003cp\u003e4.4. Synchronous Link DRAMs (SLDRAMs) 275\u003c\/p\u003e \u003cp\u003e4.4.1. SLDRAM Standard 277\u003c\/p\u003e \u003cp\u003e4.4.2. SLDRAM Architectural and Functional Overview 283\u003c\/p\u003e \u003cp\u003e4.4.3. SLDRAM (Example) 285\u003c\/p\u003e \u003cp\u003e4.5. 3-D RAM 296\u003c\/p\u003e \u003cp\u003e4.5.1. Pixel ALU Operations 305\u003c\/p\u003e \u003cp\u003e4.6. Memory System Design Considerations 309\u003c\/p\u003e \u003cp\u003eReferences 316\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 ADVANCED NONVOLATILE MEMORY DESIGNS AND TECHNOLOGIES 319\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1. Nonvolatile Memory Advances 319\u003c\/p\u003e \u003cp\u003e5.1.1. Introduction 319\u003c\/p\u003e \u003cp\u003e5.1.2. Serial EEPROMs 323\u003c\/p\u003e \u003cp\u003e5.1.3. Flash Memory Developments 327\u003c\/p\u003e \u003cp\u003e5.2. Floating Gate Cell Theory and Operations 334\u003c\/p\u003e \u003cp\u003e5.2.1. Floating Gate Cell Theory 334\u003c\/p\u003e \u003cp\u003e5.2.2. Charge Transport Mechanisms 339\u003c\/p\u003e \u003cp\u003e5.2.2.1. Fowler-Nordheim Tunneling 340\u003c\/p\u003e \u003cp\u003e5.2.2.2. Polyoxide Conduction 342\u003c\/p\u003e \u003cp\u003e5.2.2.3. Channel Hot-Electron Injection (CHEI) 343\u003c\/p\u003e \u003cp\u003e5.2.2.4. Direct Band-to-Band Tunneling 347\u003c\/p\u003e \u003cp\u003e5.3. Nonvolatile Memory Cell and Array Designs 350\u003c\/p\u003e \u003cp\u003e5.3.1. UV-EPROM (or EPROM) Cells 350\u003c\/p\u003e \u003cp\u003e5.3.1.1. T-Cell EPROM 351\u003c\/p\u003e \u003cp\u003e5.3.1.2. X-Cell EPROM 351\u003c\/p\u003e \u003cp\u003e5.3.1.3. Staggered Virtual Ground (SVG) Cell Array EPROM 352\u003c\/p\u003e \u003cp\u003e5.3.1.4. Alternate Metal Virtual Ground (AMG) Cell Array EPROM 353\u003c\/p\u003e \u003cp\u003e5.3.2. EEPROM Cells 354\u003c\/p\u003e \u003cp\u003e5.3.3. Flash Memory Cells 354\u003c\/p\u003e \u003cp\u003e5.3.3.1. T-Cell Flash 355\u003c\/p\u003e \u003cp\u003e5.3.3.2. Alternate Metal Ground (AMG) Flash Cell 357\u003c\/p\u003e \u003cp\u003e5.3.3.3. Source-Coupled Split-Gate (SCSG) Flash Cell 358\u003c\/p\u003e \u003cp\u003e5.3.3.4. Field-Enhancing Tunneling Injector Flash Cell 359\u003c\/p\u003e \u003cp\u003e5.3.3.5. Triple-Polysilicon Virtual Ground (TPVG) Flash Cell 362\u003c\/p\u003e \u003cp\u003e5.3.3.6. Divided Bit-Line NOR (DINOR) Flash Cell 363\u003c\/p\u003e \u003cp\u003e5.3.3.7. AND Flash Cell 365\u003c\/p\u003e \u003cp\u003e5.3.3.8. High Capacitive Coupling Ratio (HiCr) Flash Cell 366\u003c\/p\u003e \u003cp\u003e5.3.3.9. NAND Flash Cell 366\u003c\/p\u003e \u003cp\u003e5.3.4. Flash Memory Cell Basic Operation and Processes 368\u003c\/p\u003e \u003cp\u003e5.3.5. Flash EEPROM Technology Developments 372\u003c\/p\u003e \u003cp\u003e5.4. Flash Memory Architectures 377\u003c\/p\u003e \u003cp\u003e5.4.1. NOR Flash Memories 378\u003c\/p\u003e \u003cp\u003e5.4.1.1. AMD NOR Architecture Flash Memories 381\u003c\/p\u003e \u003cp\u003e5.4.1.2. Intel Flash Memories 387\u003c\/p\u003e \u003cp\u003e5.4.2. NAND Flash Memories 392\u003c\/p\u003e \u003cp\u003e5.4.2.1. AMD NAND Architecture Flash Memories 393\u003c\/p\u003e \u003cp\u003e5.4.2.2. Samsung 32M x 8-bit NAND Architecture Flash Memory 397\u003c\/p\u003e \u003cp\u003e5.4.2.3. Virtual DRAM 401\u003c\/p\u003e \u003cp\u003e5.4.3. DINOR Architecture Flash Memories 403\u003c\/p\u003e \u003cp\u003e5.4.3.1. A 16-Mb DINOR Flash Memory 405\u003c\/p\u003e \u003cp\u003e5.4.3.2. P-Channel DINOR Flash Memory 406\u003c\/p\u003e \u003cp\u003e5.4.3.3. BiNOR Cell Flash Memory 408\u003c\/p\u003e \u003cp\u003e5.4.4. AND Architecture Flash Memories 410\u003c\/p\u003e \u003cp\u003e5.4.5. Specialty Flash Memories 411\u003c\/p\u003e \u003cp\u003e5.5. Multilevel Nonvolatile Memories 412\u003c\/p\u003e \u003cp\u003e5.5.1. Multilevel NOR Flash Memories 418\u003c\/p\u003e \u003cp\u003e5.5.2. Multilevel NAND Flash Memories 426\u003c\/p\u003e \u003cp\u003e5.5.2.1. A 512-Mb NAND Flash Memory 429\u003c\/p\u003e \u003cp\u003e5.5.3. Multilevel AND Flash Memories 429\u003c\/p\u003e \u003cp\u003e5.6. Flash Memory Reliability Issues 430\u003c\/p\u003e \u003cp\u003e5.6.1. General Failure Mechanisms for EPROMsEEPROMs 430\u003c\/p\u003e \u003cp\u003e5.6.1.1. Stuck Bit 434\u003c\/p\u003e \u003cp\u003e5.6.1.2. Data Retention Degradation 434\u003c\/p\u003e \u003cp\u003e5.6.1.3. Read Time Degradation 434\u003c\/p\u003e \u003cp\u003e5.6.1.4. Erase Time Degradation 434\u003c\/p\u003e \u003cp\u003e5.6.1.5. Program Time Degradation 434\u003c\/p\u003e \u003cp\u003e5.6.1.6. Disturbs 434\u003c\/p\u003e \u003cp\u003e5.6.2. Flash Memory Reliability 435\u003c\/p\u003e \u003cp\u003e5.6.2.1. Flash Overerase 436\u003c\/p\u003e \u003cp\u003e5.6.2.2. Flash Program Disturbs 436\u003c\/p\u003e \u003cp\u003e5.6.2.3. Flash Read Disturbs 437\u003c\/p\u003e \u003cp\u003e5.6.2.4. Flash ProgramErase Endurance 437\u003c\/p\u003e \u003cp\u003e5.6.2.5. Flash Data Retention Failures 439\u003c\/p\u003e \u003cp\u003e5.6.2.6. Flash Hot Carrier Reliability Effects 441\u003c\/p\u003e \u003cp\u003e5.6.2.7. Multilevel Flash Reliability 442\u003c\/p\u003e \u003cp\u003e5.7. Ferroelectric Memories 443\u003c\/p\u003e \u003cp\u003e5.7.1. Technology Overview 443\u003c\/p\u003e \u003cp\u003e5.7.2. Ferroelectric Materials and Memory Design 451\u003c\/p\u003e \u003cp\u003e5.7.3. Megabit FRAMs 454\u003c\/p\u003e \u003cp\u003e5.7.4. Chain FRAM (CFRAM) 463\u003c\/p\u003e \u003cp\u003e5.7.5. Metal Ferroelectric Semiconductor FET 465\u003c\/p\u003e \u003cp\u003e5.7.6. FRAM Reliability Issues 467\u003c\/p\u003e \u003cp\u003eReferences 469\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 EMBEDDED MEMORIES DESIGNS AND APPLICATIONS 479\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1. Embedded Memory Developments 479\u003c\/p\u003e \u003cp\u003e6.2. Cache Memory Designs 487\u003c\/p\u003e \u003cp\u003e6.2.1. Cache Architecture Implementation for a DSP (Example) 495\u003c\/p\u003e \u003cp\u003e6.3. Embedded SRAMDRAM Designs 499\u003c\/p\u003e \u003cp\u003e6.3.1. Embedded SRAM Macros 503\u003c\/p\u003e \u003cp\u003e6.3.1.1. A IT SRAM Macro 504\u003c\/p\u003e \u003cp\u003e6.3.1.2. A 4T SRAM Macro 506\u003c\/p\u003e \u003cp\u003e6.3.2. Embedded DRAM Macros 508\u003c\/p\u003e \u003cp\u003e6.3.2.1. dRAMASICs 508\u003c\/p\u003e \u003cp\u003e6.3.2.2. A Compiled 100-MHz DRAM Macro 509\u003c\/p\u003e \u003cp\u003e6.3.2.3. A Dual-Port Interleaved DRAM Architecture Macro 511\u003c\/p\u003e \u003cp\u003e6.3.2.4. A 1-GHz Synchronous DRAM Macro 513\u003c\/p\u003e \u003cp\u003e6.4. Merged Processor DRAM Architectures 516\u003c\/p\u003e \u003cp\u003e6.5. DRAM Processes with Embedded Logic Architectures 522\u003c\/p\u003e \u003cp\u003e6.5.1. A Modular Embedded DRAM Core 523\u003c\/p\u003e \u003cp\u003e6.5.2. Multimedia Accelerator with Embedded DRAM 524\u003c\/p\u003e \u003cp\u003e6.5.3. Intelligent RAM (IRAM) 527\u003c\/p\u003e \u003cp\u003e6.5.4. Computational RAM 530\u003c\/p\u003e \u003cp\u003e6.6. Embedded EEPROM and Flash Memories 533\u003c\/p\u003e \u003cp\u003e6.7. Memory Cards and MultiMedia Applications 536\u003c\/p\u003e \u003cp\u003e6.7.1. Memory Cards 536\u003c\/p\u003e \u003cp\u003e6.7.2. Single-Chip Flash Disk 544\u003c\/p\u003e \u003cp\u003eReferences 547\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 FUTURE MEMORY DIRECTIONS: MEGABYTES TO TERABYTES 549\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1. Future Memory Developments 549\u003c\/p\u003e \u003cp\u003e7.2. Magnetoresistive Random Access Memories (MRAMs) 551\u003c\/p\u003e \u003cp\u003e7.2.1. MRAM Technology Developments and Tradeoffs 551\u003c\/p\u003e \u003cp\u003e7.2.2. MRAM Cells and Architectures 556\u003c\/p\u003e \u003cp\u003e7.2.3. 256K1-Mb GMRAMs 566\u003c\/p\u003e \u003cp\u003e7.2.4. Multilevel MRAMs 571\u003c\/p\u003e \u003cp\u003e7.3. Resonant Tunneling Diode-Based Memories 572\u003c\/p\u003e \u003cp\u003e7.3.1. Resonant Tuneling Diode Theory 572\u003c\/p\u003e \u003cp\u003e7.3.2. Tunneling SRAM (TSRAM) Cell Designs 574\u003c\/p\u003e \u003cp\u003e7.3.3. RTD-Based Memory System (Example) 579\u003c\/p\u003e \u003cp\u003e7.4. Single-Electron Memories 582\u003c\/p\u003e \u003cp\u003e7.4.1. Single-Electron Device Theory 582\u003c\/p\u003e \u003cp\u003e7.4.2. Single-Electron Memory Characteristics and Configurations 590\u003c\/p\u003e \u003cp\u003e7.4.3. Single-Electron Devices Fabrication Techniques 595\u003c\/p\u003e \u003cp\u003e7.4.4. Nanocrystal Memory Devices 596\u003c\/p\u003e \u003cp\u003e7.5. Phase-Change Nonvolatile Memories 602\u003c\/p\u003e \u003cp\u003e7.6. Protonic Nonvolatile Memories 607\u003c\/p\u003e \u003cp\u003e7.7. Miscellaneous Memory Technology Development (Examples) 612\u003c\/p\u003e \u003cp\u003e7.7.1. Thyristor-Based SRAM Cell (T-RAM) 613\u003c\/p\u003e \u003cp\u003e7.7.2. Content Addressable Read-Only Memory (CAROM) 614\u003c\/p\u003e \u003cp\u003e7.7.3. Nanotech Memories 618\u003c\/p\u003e \u003cp\u003e7.7.4. Solid-State Holographic Memories 618\u003c\/p\u003e \u003cp\u003eReferences 623\u003c\/p\u003e \u003cp\u003eINDEX 631\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52286308811032,"sku":"9780471208136","price":178.95,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471208136.jpg?v=1781549534","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/advanced-semiconductor-memories-architectures-designs-and-applications-hardback-9780471208136","provider":"Freshly Printed Books","version":"1.0","type":"link"}