{"product_id":"advanced-integrated-communication-microsystems-hardback-9780471709602","title":"Advanced Integrated Communication Microsystems (Hardback) 9780471709602","description":"\u003cfont face=\"Georgia\"\u003e\r\n\u003cp\u003e\u003cfont size=\"6\"\u003eAdvanced Integrated Communication Microsystems\u003c\/font\u003e\u003cbr\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003c\/p\u003e\n\u003cp\u003e\u003cfont size=\"4\"\u003eJoy Laskar (Author), Sudipto Chakraborty (Author), Anh-Vu Pham (Author), Manos M. Tantzeris (Author)\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e9780471709602, Wiley\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eHardback, published 20 March 2009\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e496 pages\u003cbr\u003e24.1 x 16 x 2.7 cm, 0.771 kg\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\r\n\r\n\r\n\u003cp align=\"justify\"\u003e\u003cstrong\u003e\u003cfont size=\"3\"\u003eLearn the fundamentals of integrated communication microsystems  \u003cp\u003eAdvanced communication microsystems—the latest technology to emerge in the semiconductor sector after microprocessors—require integration of diverse signal processing blocks in a power-efficient and cost-effective manner. Typically, these systems include data acquisition, data processing, telemetry, and power management. The overall development is a synergy among system, circuit, and component-level designs with a strong emphasis on integration.\u003c\/p\u003e \u003cp\u003eThis book is targeted at students, researchers, and industry practitioners in the semiconductor area who require a thorough understanding of integrated communication microsystems from a developer's perspective. The book thoroughly and carefully explores:\u003c\/p\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eFundamental requirements of communication microsystems\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eSystem design and considerations for wired and wireless communication microsystems\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eAdvanced block-level design techniques for communication microsystems\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eIntegration of communication systems in a hybrid environment\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003ePackaging considerations\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003ePower and form factor trade-offs in building integrated microsystems\u003c\/p\u003e \u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eAdvanced Integrated Communication Microsystems is an ideal textbook for advanced undergraduate and graduate courses. It also serves as a valuable reference for researchers and practitioners in circuit design for telecommunications and related fields.\u003c\/p\u003e\u003c\/font\u003e\u003c\/strong\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003e\u003cp\u003ePreface xv\u003c\/p\u003e \u003cp\u003eAcknowledgments xix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Fundamental Concepts and Background 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 1\u003c\/p\u003e \u003cp\u003e1.1 Communication Systems 1\u003c\/p\u003e \u003cp\u003e1.2 History and Overview of Wireless Communication Systems 3\u003c\/p\u003e \u003cp\u003e1.3 History and Overview of Wired Communication Systems 4\u003c\/p\u003e \u003cp\u003e1.4 Communication System Fundamentals 5\u003c\/p\u003e \u003cp\u003e1.4.1 Channel Capacity 5\u003c\/p\u003e \u003cp\u003e1.4.2 Bandwidth and Power Tradeoff 6\u003c\/p\u003e \u003cp\u003e1.4.3 SNR as a Metric 7\u003c\/p\u003e \u003cp\u003e1.4.4 Operating Frequency 8\u003c\/p\u003e \u003cp\u003e1.4.5 The Cellular Concept 9\u003c\/p\u003e \u003cp\u003e1.4.6 Digital Communications 10\u003c\/p\u003e \u003cp\u003e1.4.7 Power Constraint 11\u003c\/p\u003e \u003cp\u003e1.4.8 Symbol Constellation 12\u003c\/p\u003e \u003cp\u003e1.4.9 Quadrature Basis and Sideband Combination 12\u003c\/p\u003e \u003cp\u003e1.4.10 Negative Frequency 13\u003c\/p\u003e \u003cp\u003e1.5 Electromagnetics 14\u003c\/p\u003e \u003cp\u003e1.5.1 Maxwell’s Equations 14\u003c\/p\u003e \u003cp\u003e1.5.2 Application to Circuit Design 14\u003c\/p\u003e \u003cp\u003e1.5.3 Signal Propagation in Wireless Medium 15\u003c\/p\u003e \u003cp\u003e1.6 Analysis of Circuits and Systems 16\u003c\/p\u003e \u003cp\u003e1.6.1 Laplace Transformation 16\u003c\/p\u003e \u003cp\u003e1.6.2 Fourier Series 16\u003c\/p\u003e \u003cp\u003e1.6.3 Fourier Transform 18\u003c\/p\u003e \u003cp\u003e1.6.4 Time and Frequency Domain Duality 18\u003c\/p\u003e \u003cp\u003e1.6.5 Z Transform 20\u003c\/p\u003e \u003cp\u003e1.6.6 Circuit Dynamics 21\u003c\/p\u003e \u003cp\u003e1.6.7 Frequency Domain and Time Domain Simulators 21\u003c\/p\u003e \u003cp\u003e1.6.8 Matrix Representation of Circuits 21\u003c\/p\u003e \u003cp\u003e1.7 Broadband, Wideband, and Narrowband Systems 26\u003c\/p\u003e \u003cp\u003e1.7.1 LC Tank as a Narrowband Element 26\u003c\/p\u003e \u003cp\u003e1.7.2 LC Tank at Resonance 27\u003c\/p\u003e \u003cp\u003e1.7.3 Q Factor, Power, and Area Metrics 28\u003c\/p\u003e \u003cp\u003e1.7.4 Silicon-Specific Considerations 28\u003c\/p\u003e \u003cp\u003e1.7.5 Time Domain Behavior 29\u003c\/p\u003e \u003cp\u003e1.7.6 Series\/Parallel Resonance 29\u003c\/p\u003e \u003cp\u003e1.8 Semiconductor Technology and Devices 30\u003c\/p\u003e \u003cp\u003e1.8.1 Silicon-Based Processes 31\u003c\/p\u003e \u003cp\u003e1.8.2 Unity Current and Power Gain 31\u003c\/p\u003e \u003cp\u003e1.8.3 Noise 33\u003c\/p\u003e \u003cp\u003e1.8.4 Bipolar vs. MOS 34\u003c\/p\u003e \u003cp\u003e1.8.5 Device Characteristics 35\u003c\/p\u003e \u003cp\u003e1.8.6 Passive Components 41\u003c\/p\u003e \u003cp\u003e1.8.7 Evaluation Testbenches 51\u003c\/p\u003e \u003cp\u003e1.9 Key Circuit Topologies 55\u003c\/p\u003e \u003cp\u003e1.9.1 Differential Circuits 55\u003c\/p\u003e \u003cp\u003e1.9.2 Translinear Circuits 58\u003c\/p\u003e \u003cp\u003e1.9.3 Feedback Circuits 59\u003c\/p\u003e \u003cp\u003e1.9.4 Cascode Circuits 61\u003c\/p\u003e \u003cp\u003e1.9.5 Common Source, Common Gate, and Common Drain Stages 62\u003c\/p\u003e \u003cp\u003e1.9.6 Folded Cascode Topology 64\u003c\/p\u003e \u003cp\u003e1.10 Gain\/Linearity\/Noise 65\u003c\/p\u003e \u003cp\u003e1.10.1 Noise and Intermodulation Tradeoff 65\u003c\/p\u003e \u003cp\u003e1.10.2 Narrowband and Wideband Systems 66\u003c\/p\u003e \u003cp\u003eConclusion 66\u003c\/p\u003e \u003cp\u003eReferences 66\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Wireless Communication System Architectures 69\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 69\u003c\/p\u003e \u003cp\u003e2.1 Fundamental Considerations 70\u003c\/p\u003e \u003cp\u003e2.1.1 Center Frequency, Modulation, and Process Technology 70\u003c\/p\u003e \u003cp\u003e2.1.2 Frequency Planning 71\u003c\/p\u003e \u003cp\u003e2.1.3 Blockers 72\u003c\/p\u003e \u003cp\u003e2.1.4 Spurs and Desensing 74\u003c\/p\u003e \u003cp\u003e2.1.5 Transmitter Leakage 74\u003c\/p\u003e \u003cp\u003e2.1.6 LO leakage and Interference 74\u003c\/p\u003e \u003cp\u003e2.1.7 Image 76\u003c\/p\u003e \u003cp\u003e2.1.8 Half-IF Interference 76\u003c\/p\u003e \u003cp\u003e2.2 Link Budget Analysis 77\u003c\/p\u003e \u003cp\u003e2.2.1 Linearity 77\u003c\/p\u003e \u003cp\u003e2.2.2 Noise 80\u003c\/p\u003e \u003cp\u003e2.2.3 Signal-to-Noise Ratio 82\u003c\/p\u003e \u003cp\u003e2.2.4 Receiver Gain 82\u003c\/p\u003e \u003cp\u003e2.3 Propagation Effects 83\u003c\/p\u003e \u003cp\u003e2.3.1 Path Loss 83\u003c\/p\u003e \u003cp\u003e2.3.2 Multipath and Fading 85\u003c\/p\u003e \u003cp\u003e2.3.3 Equalization 86\u003c\/p\u003e \u003cp\u003e2.3.4 Diversity 86\u003c\/p\u003e \u003cp\u003e2.3.5 Coding 87\u003c\/p\u003e \u003cp\u003e2.4 Interface Planning 87\u003c\/p\u003e \u003cp\u003e2.5 Superheterodyne Architecture 87\u003c\/p\u003e \u003cp\u003e2.5.1 Frequency Domain Representation 88\u003c\/p\u003e \u003cp\u003e2.5.2 Phase Shift and Image Rejection 89\u003c\/p\u003e \u003cp\u003e2.5.3 Transmitter and Receiver 90\u003c\/p\u003e \u003cp\u003e2.5.4 Imbalance and Harmonics 90\u003c\/p\u003e \u003cp\u003e2.6 Low IF Architecture 91\u003c\/p\u003e \u003cp\u003e2.7 Direct Conversion Architecture 92\u003c\/p\u003e \u003cp\u003e2.7.1 Advantages 93\u003c\/p\u003e \u003cp\u003e2.7.2 Modulation 93\u003c\/p\u003e \u003cp\u003e2.7.3 Architecture and Frequency Planning 93\u003c\/p\u003e \u003cp\u003e2.7.4 Challenges in the Direct Conversion Receiver 94\u003c\/p\u003e \u003cp\u003e2.8 Two-Stage Direct Conversion 102\u003c\/p\u003e \u003cp\u003e2.9 Current-Mode Architecture 103\u003c\/p\u003e \u003cp\u003e2.10 Subsampling Architecture 104\u003c\/p\u003e \u003cp\u003e2.11 Multiband Direct Conversion Radio 105\u003c\/p\u003e \u003cp\u003e2.12 Polar Modulator 106\u003c\/p\u003e \u003cp\u003e2.13 Harmonic Reject Architecture 108\u003c\/p\u003e \u003cp\u003e2.14 Practical Considerations for Transceiver Integration 109\u003c\/p\u003e \u003cp\u003e2.14.1 Transmitter Considerations 109\u003c\/p\u003e \u003cp\u003e2.14.2 Receiver Considerations 110\u003c\/p\u003e \u003cp\u003eConclusion 111\u003c\/p\u003e \u003cp\u003eReferences 111\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 System Architecture for High-Speed Wired Communications 113\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 113\u003c\/p\u003e \u003cp\u003e3.1 Bandlimited Channel 118\u003c\/p\u003e \u003cp\u003e3.1.1 Fiber Optical Link 118\u003c\/p\u003e \u003cp\u003e3.1.2 Dispersion in Fibers 120\u003c\/p\u003e \u003cp\u003e3.1.3 Backplane Multi-Gb\/s Data Interface 123\u003c\/p\u003e \u003cp\u003e3.1.4 Backplane Channel Loss 124\u003c\/p\u003e \u003cp\u003e3.2 Equalizer System Study 129\u003c\/p\u003e \u003cp\u003e3.2.1 Equalization Overview 129\u003c\/p\u003e \u003cp\u003e3.2.2 Historical Background 131\u003c\/p\u003e \u003cp\u003e3.2.3 Equalizer Topology Study 133\u003c\/p\u003e \u003cp\u003e3.2.4 Equalizer System Simulation 139\u003c\/p\u003e \u003cp\u003eConclusion 143\u003c\/p\u003e \u003cp\u003eReferences 143\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Mixed Building Blocks of Signal Communication Systems 144\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 144\u003c\/p\u003e \u003cp\u003e4.1 Inverters 145\u003c\/p\u003e \u003cp\u003e4.1.1 Key Design Parameters 145\u003c\/p\u003e \u003cp\u003e4.1.2 Key Electrical Equations 146\u003c\/p\u003e \u003cp\u003e4.1.3 Current Reuse Amplifier 147\u003c\/p\u003e \u003cp\u003e4.1.4 Cascade and Fan-Out 148\u003c\/p\u003e \u003cp\u003e4.2 Static D Flip-Flop 148\u003c\/p\u003e \u003cp\u003e4.3 Bias Circuits 151\u003c\/p\u003e \u003cp\u003e4.3.1 Current Sources and Sinks 151\u003c\/p\u003e \u003cp\u003e4.3.2 Voltage References 153\u003c\/p\u003e \u003cp\u003e4.4 Transconductor Cores 154\u003c\/p\u003e \u003cp\u003e4.5 Load Networks 157\u003c\/p\u003e \u003cp\u003e4.5.1 Passive Load 157\u003c\/p\u003e \u003cp\u003e4.5.2 Active Load 158\u003c\/p\u003e \u003cp\u003e4.6 AVersatile Analog Signal Processing Core 159\u003c\/p\u003e \u003cp\u003e4.7 Low Noise Amplifier 162\u003c\/p\u003e \u003cp\u003e4.7.1 Single-Ended Interfaces 163\u003c\/p\u003e \u003cp\u003e4.7.2 Design Steps 163\u003c\/p\u003e \u003cp\u003e4.7.3 Gain Expansion 165\u003c\/p\u003e \u003cp\u003e4.7.4 Layout Considerations 165\u003c\/p\u003e \u003cp\u003e4.7.5 Inductorless LNAs 166\u003c\/p\u003e \u003cp\u003e4.7.6 Gain Variation 166\u003c\/p\u003e \u003cp\u003e4.8 Power Amplifiers 168\u003c\/p\u003e \u003cp\u003e4.8.1 Performance Metrics 168\u003c\/p\u003e \u003cp\u003e4.8.2 Classes of Amplifiers 170\u003c\/p\u003e \u003cp\u003e4.8.3 Practical Considerations 172\u003c\/p\u003e \u003cp\u003e4.8.4 PA Architectures 172\u003c\/p\u003e \u003cp\u003e4.8.5 Feedback and Feedforward 174\u003c\/p\u003e \u003cp\u003e4.8.6 Predistortion Techniques 177\u003c\/p\u003e \u003cp\u003e4.9 Balun 178\u003c\/p\u003e \u003cp\u003e4.10 Signal Generation Path 179\u003c\/p\u003e \u003cp\u003e4.10.1 Oscillator Circuits 179\u003c\/p\u003e \u003cp\u003e4.10.2 Quadrature Generation Networks 188\u003c\/p\u003e \u003cp\u003e4.10.3 Passive Hybrid Networks 194\u003c\/p\u003e \u003cp\u003e4.10.4 Regenerative Frequency Dividers 194\u003c\/p\u003e \u003cp\u003e4.10.5 Phase Locked Loop 195\u003c\/p\u003e \u003cp\u003e4.11 Mixers 201\u003c\/p\u003e \u003cp\u003e4.11.1 Basic Functionality 201\u003c\/p\u003e \u003cp\u003e4.11.2 Architectures 202\u003c\/p\u003e \u003cp\u003e4.11.3 Conversion Gain\/Loss 203\u003c\/p\u003e \u003cp\u003e4.11.4 Noise 204\u003c\/p\u003e \u003cp\u003e4.11.5 Port Isolation 205\u003c\/p\u003e \u003cp\u003e4.11.6 Receive and Transmit Mixers 205\u003c\/p\u003e \u003cp\u003e4.11.7 Impedances 206\u003c\/p\u003e \u003cp\u003e4.12 Baseband Filters 207\u003c\/p\u003e \u003cp\u003e4.12.1 Classification of Integrated Filters 207\u003c\/p\u003e \u003cp\u003e4.12.2 Biquadratic Stages 208\u003c\/p\u003e \u003cp\u003e4.12.3 Switched Capacitor Filters 209\u003c\/p\u003e \u003cp\u003e4.12.4 Gm-C Filters 211\u003c\/p\u003e \u003cp\u003e4.12.5 OP-Amp-RC Filters 213\u003c\/p\u003e \u003cp\u003e4.12.6 Calibration of On-Chip Filters 224\u003c\/p\u003e \u003cp\u003e4.12.7 Passive Filter Configuration 226\u003c\/p\u003e \u003cp\u003e4.13 Signal Strength Indicator (SSI) 226\u003c\/p\u003e \u003cp\u003e4.14 ADC\/DAC 227\u003c\/p\u003e \u003cp\u003e4.15 Latch 230\u003c\/p\u003e \u003cp\u003eConclusion 231\u003c\/p\u003e \u003cp\u003eReferences 231\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Examples of Integrated Communication Microsystems 235\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 235\u003c\/p\u003e \u003cp\u003e5.1 Direct Conversion Receiver Front End 235\u003c\/p\u003e \u003cp\u003e5.1.1 Circuit Design 236\u003c\/p\u003e \u003cp\u003e5.1.2 The Integration: Interfaces and Layout 242\u003c\/p\u003e \u003cp\u003e5.1.3 Compensation and Corrections 243\u003c\/p\u003e \u003cp\u003e5.2 Debugging: A Practical Scenario 244\u003c\/p\u003e \u003cp\u003e5.3 High-Speed Wired Communication Example 245\u003c\/p\u003e \u003cp\u003e5.3.1. Bandlimited Channel 245\u003c\/p\u003e \u003cp\u003e5.3.2 Design Example 247\u003c\/p\u003e \u003cp\u003eConclusion 258\u003c\/p\u003e \u003cp\u003eReferences 258\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Low-Voltage, Low-Power, and Low-Area Designs 260\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 260\u003c\/p\u003e \u003cp\u003e6.1. Power Consumption Considerations 261\u003c\/p\u003e \u003cp\u003e6.1.1 Active Inductors 261\u003c\/p\u003e \u003cp\u003e6.1.2 Adding Transfer Function Zero 263\u003c\/p\u003e \u003cp\u003e6.1.3 Driving Point Impedance 263\u003c\/p\u003e \u003cp\u003e6.1.4 Stacking Functional Blocks 265\u003c\/p\u003e \u003cp\u003e6.2 Device Technology and Scaling 266\u003c\/p\u003e \u003cp\u003e6.2.1 Digital and Analog Circuits 266\u003c\/p\u003e \u003cp\u003e6.2.2 Supply Voltage, Speed, and Breakdown 266\u003c\/p\u003e \u003cp\u003e6.2.3 Circuit Impacts of Increased fT 267\u003c\/p\u003e \u003cp\u003e6.2.4 MOSFETs in Weak Inversion 267\u003c\/p\u003e \u003cp\u003e6.2.5 Millimeter-Wave Applications 268\u003c\/p\u003e \u003cp\u003e6.2.6 Practical Considerations 268\u003c\/p\u003e \u003cp\u003e6.3 Low-Voltage Design Techniques 269\u003c\/p\u003e \u003cp\u003e6.3.1 Separate DC Paths per Circuit Functionality 269\u003c\/p\u003e \u003cp\u003e6.3.2 Transformer Coupled Feedback 270\u003c\/p\u003e \u003cp\u003e6.3.3 Positive Feedback 271\u003c\/p\u003e \u003cp\u003e6.3.4 Current-Mode Interface 272\u003c\/p\u003e \u003cp\u003e6.3.5 Circuits Based on Weak Inversion 273\u003c\/p\u003e \u003cp\u003e6.3.6 Voltage Boosting 273\u003c\/p\u003e \u003cp\u003e6.3.7 Bulk-Driven Circuits 274\u003c\/p\u003e \u003cp\u003e6.3.8 Flipped Voltage Follower 276\u003c\/p\u003e \u003cp\u003e6.4 Injection-Locked Techniques 277\u003c\/p\u003e \u003cp\u003e6.5. Subharmonic Architectures 279\u003c\/p\u003e \u003cp\u003e6.5.1 Formalism 279\u003c\/p\u003e \u003cp\u003e6.5.2 System Considerations 280\u003c\/p\u003e \u003cp\u003e6.5.3 Antiparallel Diode Pair 281\u003c\/p\u003e \u003cp\u003e6.5.4 Active Subharmonic Mixers 284\u003c\/p\u003e \u003cp\u003e6.5.5 Subharmonic Architecture Building Blocks 286\u003c\/p\u003e \u003cp\u003e6.6. Super-Regenerative Architectures 286\u003c\/p\u003e \u003cp\u003e6.6.1 Formalism 287\u003c\/p\u003e \u003cp\u003e6.6.2 Architecture and Circuit Illustration 289\u003c\/p\u003e \u003cp\u003e6.7. Hearing Aid Applications 290\u003c\/p\u003e \u003cp\u003e6.7.1 Architecture Based on Digital\/Mixed-Signal Circuits 290\u003c\/p\u003e \u003cp\u003e6.7.2 Architecture Based on Subthreshold Current-Mode Circuits 292\u003c\/p\u003e \u003cp\u003e6.8. Radio Frequency Identification Tags 297\u003c\/p\u003e \u003cp\u003e6.8.1 System Considerations 297\u003c\/p\u003e \u003cp\u003e6.8.2 System Architecture 297\u003c\/p\u003e \u003cp\u003e6.8.3 Rectifier, Limiter, and Regulator 298\u003c\/p\u003e \u003cp\u003e6.8.4 Antenna Design 301\u003c\/p\u003e \u003cp\u003e6.9. Ultra-Low-Power Radios 302\u003c\/p\u003e \u003cp\u003eConclusion 303\u003c\/p\u003e \u003cp\u003eReferences 304\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Packaging for Integrated Communication Microsystems 309\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 309\u003c\/p\u003e \u003cp\u003e7.1. Background 311\u003c\/p\u003e \u003cp\u003e7.1.1 Trends from 1970 to 1995 311\u003c\/p\u003e \u003cp\u003e7.1.2 Trends from 1995 to Today 313\u003c\/p\u003e \u003cp\u003e7.1.3 Before 2006 314\u003c\/p\u003e \u003cp\u003e7.1.4 After 2006 314\u003c\/p\u003e \u003cp\u003e7.2 Elements of a Package 315\u003c\/p\u003e \u003cp\u003e7.2.1 Power\/GND Planes 315\u003c\/p\u003e \u003cp\u003e7.2.2 Package Materials 317\u003c\/p\u003e \u003cp\u003e7.3 Current Chip Packaging Technologies 317\u003c\/p\u003e \u003cp\u003e7.3.1 Ball Grid Arrays (BGAs) 317\u003c\/p\u003e \u003cp\u003e7.3.2 Flip-Chip Technology (FCT) 319\u003c\/p\u003e \u003cp\u003e7.3.3 Flip-Chip vs. Wire Bond 319\u003c\/p\u003e \u003cp\u003e7.3.4 Choice of Transmission Line 320\u003c\/p\u003e \u003cp\u003e7.3.5 Thermal Issues 320\u003c\/p\u003e \u003cp\u003e7.3.6 Chip Scale Packaging (CSP) 321\u003c\/p\u003e \u003cp\u003e7.4 Driving Forces for RF Packaging Technology 322\u003c\/p\u003e \u003cp\u003e7.5 MCM Definitions and Classifications 323\u003c\/p\u003e \u003cp\u003e7.6 RF–SOP Modules 325\u003c\/p\u003e \u003cp\u003e7.7 Package Modeling and Optimization 329\u003c\/p\u003e \u003cp\u003e7.8 Future Packaging Trends 333\u003c\/p\u003e \u003cp\u003e7.9 Chip-Package Codesign 334\u003c\/p\u003e \u003cp\u003e7.10 Package Models and Transmission Lines 335\u003c\/p\u003e \u003cp\u003e7.10.1 Frequency of Operations 335\u003c\/p\u003e \u003cp\u003e7.10.2 Bends and Discontinuities 336\u003c\/p\u003e \u003cp\u003e7.10.3 Differential Signaling 337\u003c\/p\u003e \u003cp\u003e7.11 Calculations for Package Elements 339\u003c\/p\u003e \u003cp\u003e7.11.1 Inductance 339\u003c\/p\u003e \u003cp\u003e7.11.2 Capacitance 340\u003c\/p\u003e \u003cp\u003e7.11.3 Image Theory 341\u003c\/p\u003e \u003cp\u003e7.12 Crosstalk 342\u003c\/p\u003e \u003cp\u003e7.13 Grounding 343\u003c\/p\u003e \u003cp\u003e7.14 Practical Issues in Packaging 344\u003c\/p\u003e \u003cp\u003e7.15 Chip-Package Codesign Examples 346\u003c\/p\u003e \u003cp\u003e7.16 Wafer Scale Package 349\u003c\/p\u003e \u003cp\u003e7.17 Filters Using Bondwire 349\u003c\/p\u003e \u003cp\u003e7.18 Packaging Limitation 350\u003c\/p\u003e \u003cp\u003eConclusion 351\u003c\/p\u003e \u003cp\u003eReferences 351\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Advanced SOP Components and Signal Processing 355\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 355\u003c\/p\u003e \u003cp\u003e8.1 History of Compact Design 358\u003c\/p\u003e \u003cp\u003e8.2 Previous Techniques in Performance Enhancement 361\u003c\/p\u003e \u003cp\u003e8.3 Design Complexities 363\u003c\/p\u003e \u003cp\u003e8.4 Modeling Complexities 363\u003c\/p\u003e \u003cp\u003e8.5 Compact Stacked Patch Antennas Using LTCC Multilayer Technology 365\u003c\/p\u003e \u003cp\u003e8.6 Suppression of Surface Waves and Radiation Pattern Improvement Using SHS Technology 378\u003c\/p\u003e \u003cp\u003e8.7 Radiation-Pattern Improvement Using a Compact Soft-Surface Structure 382\u003c\/p\u003e \u003cp\u003e8.8 A Package-Level-Integrated Antenna Based on LTCC Technology 395\u003c\/p\u003e \u003cp\u003eConclusion 401\u003c\/p\u003e \u003cp\u003eReferences 401\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Simulation and Characterization of Integrated Microsystems 404\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction 404\u003c\/p\u003e \u003cp\u003e9.1 Computer-Aided Analysis of Wireless Systems 404\u003c\/p\u003e \u003cp\u003e9.1.1 Operating Point Analysis 405\u003c\/p\u003e \u003cp\u003e9.1.2 Impedance Matching 407\u003c\/p\u003e \u003cp\u003e9.1.3 Tuning at Resonance 407\u003c\/p\u003e \u003cp\u003e9.1.4 Transient Analysis 408\u003c\/p\u003e \u003cp\u003e9.1.5 Noise Analysis 409\u003c\/p\u003e \u003cp\u003e9.1.6 Linearity Analysis 410\u003c\/p\u003e \u003cp\u003e9.1.7 Parasitic Elements 413\u003c\/p\u003e \u003cp\u003e9.1.8 Process Variation 413\u003c\/p\u003e \u003cp\u003e9.2 Measurement Equipments and their Operation 413\u003c\/p\u003e \u003cp\u003e9.2.1 DC\/Operating Point 413\u003c\/p\u003e \u003cp\u003e9.2.2 C–V Measurement 414\u003c\/p\u003e \u003cp\u003e9.2.3 Vector Network Analyzer and S-Parameter Measurements 415\u003c\/p\u003e \u003cp\u003e9.2.4 Spectrum Analyzer (SA) 416\u003c\/p\u003e \u003cp\u003e9.3 Network Analyzer Calibration 418\u003c\/p\u003e \u003cp\u003e9.3.1 Overview of Network Analyzer Calibration 418\u003c\/p\u003e \u003cp\u003e9.3.2 Types of Calibration 420\u003c\/p\u003e \u003cp\u003e9.3.3 SOLT Calibration 420\u003c\/p\u003e \u003cp\u003e9.3.4. TRL Calibration 424\u003c\/p\u003e \u003cp\u003e9.4 Wafer Probing Measurement 429\u003c\/p\u003e \u003cp\u003e9.4.1 Calibration Quantification of Random Errors 429\u003c\/p\u003e \u003cp\u003e9.4.2 On-Wafer Measurement at the W-Band (75–110 GHz) 430\u003c\/p\u003e \u003cp\u003e9.4.3 On-Wafer Microstrip Characterization Techniques 435\u003c\/p\u003e \u003cp\u003e9.4.4 On-Wafer Package Characterization Technique 440\u003c\/p\u003e \u003cp\u003e9.5 Characterization of Integrated Radios 448\u003c\/p\u003e \u003cp\u003e9.6 In the Lab 451\u003c\/p\u003e \u003cp\u003e9.6.1 Operating Point 451\u003c\/p\u003e \u003cp\u003e9.6.2 Functionality Test 451\u003c\/p\u003e \u003cp\u003e9.6.3 Impedance Matching 451\u003c\/p\u003e \u003cp\u003e9.6.4 Conversion Gain 453\u003c\/p\u003e \u003cp\u003e9.6.5 Linearity 453\u003c\/p\u003e \u003cp\u003e9.6.6 Nonlinear Noise Figure 454\u003c\/p\u003e \u003cp\u003e9.6.7 I\/Q Imbalance 455\u003c\/p\u003e \u003cp\u003e9.6.8 DC Offset 456\u003c\/p\u003e \u003cp\u003eConclusion 457\u003c\/p\u003e \u003cp\u003eReferences 458\u003c\/p\u003e \u003cp\u003eAppendix A Compendium of the TRL Calibration Algorithm 459\u003c\/p\u003e \u003cp\u003eAppendix A 462\u003c\/p\u003e \u003cp\u003eIndex 469\u003c\/p\u003e\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\u003cp\u003e\u003cfont size=\"3\"\u003eSubject Areas: Electronics \u0026amp; communications engineering [\u003ca title=\"See our other books on Electronics \u0026amp; communications engineering\" href=\"https:\/\/freshlyprintedbooks.co.uk\/search?q=%22Electronics%20\u0026amp;%20communications%20engineering%20%5BTJ%5D%22\"\u003eTJ\u003c\/a\u003e]\u003c\/font\u003e\u003c\/p\u003e\r\n\r\n\r\n\u003c\/font\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Brand New","offer_id":52298041622808,"sku":"9780471709602","price":93.38,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0730\/2037\/5320\/files\/9780471709602.jpg?v=1781732195","url":"https:\/\/freshlyprintedbooks.co.uk\/products\/advanced-integrated-communication-microsystems-hardback-9780471709602","provider":"Freshly Printed Books","version":"1.0","type":"link"}